Casio MP-2000 Service Manual page 52

CRT & Clock Interface
Pin # Pin Name
65 HYSNC (CSYNC)
64 VSYNC (VISINT)
60 RED
58 GREEN
57 BLUE
55 RSET
59 AVCC
56 AGND
203 XTALI (MCLK)
204 (Reserved)
205 CVCC0
202 CGND0
206 CVCCI
208 CGND1
154 32KHz (GPIO2) (AA9)
Type Active Description
OUT Both CRT Horizontal Sync (polarity is programmable) or
"Composite Sync" for support of various external NTSC/
PAL encoder chips. Note CSYNC can be set to output on
the ACTI or ENABKL pins.
OUT Both CRT Vertical Sync (polarity is programmable) or "VSync
Interval" for support of various external NTSC 1 PAL
encoder chips.
OUT High CRT analog video outputs from the internal color palette
OUT High DAC. The DAC is designed for a 37.5Ω equivalent load on
OUT High each pin (e.g. 75Ω resistor on the board, in parallel with the
75Ω CRT load).
In N/A Set point resistor for the internal color palette DAC. A 590
Ω 1% resistor is acquired between RSET and AGND.
VCC - Analog power and ground pins for noise isolation for the
GND - internal color palette DAC. AVCC should be isolated from
digital VCC as described in the Functional Description of
the internal color palette DAC. For proper DAC operation.
AVCC should not be greater than IVCC. AGND should be
common with digital ground but must be tightly decoupled
to AVCC. See the Functional Description of the internal
color palette DAC for further information.
In High Crystal In. This pin serves as the input for an extemal
reference oscillator (usually 14.31818 MHz). Note that in
test mode for the internal clock synthesizer, MCLK is
output on A25 (pin 30) and VCLK is output on A24 (pin
29).
Reserved. For compatibility with the 65545, this pin
(formerly "Crystal Out" or "XTLAO") must be discon-
nected. In addition, pin 150 must be pulled down on reset.
The 65545 no longer supports the "internal oscillator"
option.
VCC - Analog power and ground pins for noise isolation for the
GND - internal clock synthesizer. Must be the same as VCC for
internal logic. VCC/GND pair 0 and VCC/GND pair 1 pins
VCC - must be carefully decoupled individually. Refer also to the
GND - section on clock ground layout in the Functional
Description. Note that the CVCC voltage must be the same
as the voltage for the internal logic (IVCC).
In High Clock input for refresh of non-self-refresh DRAMS and
panel power sequencing. This pin can be programmed as
GP102 instead of 32KHz input, or AA9 for 512Kx32
memory configurations.
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