Casio MP-2000 Service Manual page 57

Pin Description
The following table lists the functions of all M5113 pins. A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4v
nominal).
Name Number
HOST Processor Interface
D0-D7 18-51, 53-56
IORJ 44
IOWJ 45
AEN 46
A0-A9 27, 29-34,
41-43
DACKA/ 28
PADCF
FDRQ 52
DACKJ 36
TC 35
UR1IRQA 38
UR2IRQA 37
FINTR 40
PINTR1 39
RESET 57
RDATAJ 16
WGATEJ 10
Type Description
I/O24 Data bus. This connection is used by the host microprocessor to transmit data
to and from the M5113. These pins are in a high Impedance state when not in
the output mode.
I I/O Read. This active low signal is issued by the host microprocessor to
indicate a read operation.
I I/O Write. This active low signal Is issued by the host microprocessor to
indicate a write operation.
I Address Enable. This active high signal indicates DMA operations on the host
data bus.
I I/O Address. These bits determine the I/O address to be accessed during IORJ
and IOWJ cycles.
I DMA Acknowledge. An active low input signal acknowledging the request for
a DMA transfer of data between the host and the printer port. This input
enables the DMA read or write internally.
O4 This active high signal is read and latched during reset active.
O24 FDC DMA request. This active high output is the DMA request for byte
transfers of data to the host. This signal is cleared on the last byte of the data
transfer by the DACKJ signal going low (or by IORJ going low if DACKJ was
already low as in demand mode.
I DMA acknowledge. This active low Input acknowledging the request for a
DMA transfer of data. This input enables the DMA read or write internally.
I Terminal Count. This signal indicates to the M5113 that data transfer is
complete. TC is only accepted when DACKJ or PDACKJ is low. In AT, TC is
active high and in PS/2 mode, TC is active low.
O24 Primary Serial Port Interrupt. UR1IRQA is a source of PSP interrupt.
Externally, it should be connected to IRQ4 on PC/AT.
O24 Secondary Serial Port Interrupt. UR2IRQA is a source of SSP interrupt.
Externally, it should be connected to IRQ3 on PC/AT.
O24 FDC Interrupt Request. This interrupt from the Floppy Disk Controller is
enabled/disabled via bit 3 of the Digital Output Register (DOR).
O24 Parallel Port Interrupt Request. This request from the Parallel Port is
enabled/disabled via bit 4 of the Parallel Port Control Register.
If EPP or ECP mode is enabled, this output is pulsed low, then released to
allow sharing of interrupts.
IS Reset. This active high signal resets the M5113 and must be valid for 500 ns
minimum. In M5113, the falling edge of reset latches the jumper configuration.
The jumper select lines must be valid 50 ns prior to this edge.
IS Read Disk Data. The active-low, raw data read from the disk is connected
here. Each falling edge represents a flux transition of the encoded data.
O36 Write Gate. This active-low, high drive output enables the write circuitry of the
selected disk drive. This signal prevents glitches during power-up and power-
down. This prevents writing to the disk when power is cycled.
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