Casio MP-2000 Service Manual page 46

Pin # Pin Name
27 STOP#
25 DEVSEL#
29 PERR# (VCLKOUT)
30 SERR# (MCLKOUT)
179 ROMA0
180 ROMA1 (GPIO3)
182 ROMA2 (GPIO4)
183 ROMA3 (GPIO5)
185 ROMA4 (GPIO6)
187 ROMA5
189 ROMA6
191 ROMA7
192 ROMA8
190 ROMA9
186 ROMA10 (GPIO7)
188 ROMA11
193 ROMA12
194 ROMA 13
196 ROMA 14
195 ROMA15
197 ROMA 16
198 ROMA 17
200 ROMOE#
199 Reserved
28 Reserved
Type Active Description
S/TS Low Stop. Indicates the current target is requesting the master to
stop the current transaction
S/TS Low Device Select. Indicates the current target has decoded its
address as the target of the current access
S/TS Low Parity Error. This signal reports data parity errors (except
for Special Cycles where SERR is used). The PERR# pin
is Sustained Tri-state. The receiving agent will drive
PERR# active two clocks after detecting a data parity error.
PERR# will be driven high for one clock before being tri-
stated as with all sustained tri-state signals. PERR# will not
report status until the chip has claimed the access by
asserting DEVSEL# and completing the data phase.
OD Low System Error. Used to report system errors where the result
will be catastrophic (address parity error, data parity errors
for Special Cycle commands, etc.). This output is actively
driven for a single PCI clock cycle synchronous to CLK and
meets the same setup and hold time requirements as all other
bused signals. SERR# is not driven high by the chip after
being asserted, but is pulled high only by a weak pull-up
provided by the system. Thus, SERR# on the PCI Bus may
take two or three clock periods to fully return to an inactive
state.
Out High BIOS ROM address outputs. See MAD8-I5 (pins 170-177)
Out High for BIOS ROM data inputs.
Out High
Out High BIOS ROMS are not normally required in portable computer
Out High designs (Graphics System BIOS code is normally included
Out High in the System BIOS ROM). However, the 65550 provides
Out High BIOS ROM interface capability for development systems
Out High and add-in card Flat Panel Graphics Controllers.
Out High
Out High Since the PCI Bus specifications require only one load on
Out High the bus for the entire graphics subsystem, the BIOS ROM
Out High interface is "through the chip". In the VL-Bus mode, the
Out High BIOS ROM interface can be an external circuit on the ISA
Out High Bus connector that does not require pins on the chip (see the
Out High Application Schematics section for details).
Out High
Out High For programming GPI03-7, see registers XR62-63
Out High
Out Low BIOS ROM Output Enable.
In n/a This pin is always an input (A20 for VL-Bus, reserved for
future use on PCI Bus). To avoid abnormal Vcc current due
to a floating input for a PCI Bus, use a 10K resistor to
ground to pull this pin low
In n/a This pin is always all input (A23 for VL-BUS, reserved for
future use on PCI Bus). To avoid abnormal Vcc current due
to a floating input for a PCI Bus, use a 10K resistor to
ground to pull this pin low.
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