Casio MP-2000 Service Manual page 43

CPU Direct / VL-Bus Interface
Pin names in parentheses (...) indicate alternate functions.
Pin # Pin Name
207 RESET
22 ADS#
31 M/IO#
11 W/R#
23 RDYRTN# for 1x Clock
config
CRESET for 2X clock config
24 LRDY#
25 LDEV#
27 LCLK
43 BE0# (BLE#)
32 BE1#
21 BE2#
10 BE3#
Type Active Description
In Low Reset For VL-Bus interfaces, connet to RESET For
direct CPU local bus interfaces, connect to the system reset
generated by the motherboard system logic for all periph-
erals (not the RESET# pin of the processor). This input is
ignored during Standby mode (STNDBY# pin low) so
that the remainder of the system (and the system bus)
may be safely powered down during Standby mode if
desired.
In Low Address Strobe. In VL-Bus and CPU local bus interfaces
ADS# indicates valid address and control signal information
is present. It is used for all decodes and to indicate the start
of a bus cycle.
In Both Memory / IO. In VL-Bus and CPU local bus interfaces
M/I0# indicates either a memory or an I/O cycle:
In Both Write / Read. This control signal indicates a write (high) or
read (low) operation. It is sampled on the rising edge of the
(internal) 1x CPU clock when ADS# is active.
In Low Ready Return. Handshaking signal in VL-Bus interface
High indicating synchronization of RDY# by the local bus master
/ controller to the processor. Upon receipt of this LCLK-
synchronous signal the chip will stop driving the bus (if a
read cycle was active) and terminate the current cycle.
Out/ Low Local Ready. Driven low during VL-Bus and CPU local
OC bus cycles to indicate the current cycle should be completed.
This signal is driven high at the end of the cycle, then tri-
stated. This pin is tri-stated during Standby mode (as are all
other bus interface outputs).
Out Low Local Device. In VL-Bus and CPU local bus interfaces, this
pin indicates that the chip owns the current cycle based on
the memory or I/O address which has been broadcast. For
VL-Bus, it is a direct output reflecting a straight address
decode. This pin is tri-stated during Standby mode (as are
all other bus interface outputs).
In Both Local Clock. In VL-Bus this pin is connected to the CPU
1x clock. In CPU local bus interfaces it is connected to the
CPU 1x or 2x clock. If the input is a 2x clock, the processor
reset signal must be connected to CRESET (pin 23) for
synchronization of the clock phase
In Low Byte Enable 0.
current cycle.
In Low Byte Enable 1.
currant cycle.
In Low Byte Enable 2.
current cycle.
In Low Byte Enable 3.
the data bus on D31:24 during the current access.
— 42 —
I = memory, O = I/O.
Indicates data transfer on D7:D0 for the
Indicates data transfer on D15:D8 for the
Indicates data transfer on D23:D16 for the
BE3# indicates that data will transfer over