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SMI#
149
FERR#
141
IGENN#
139
DIORA#
50
DIOWA#
51
DIORB#
54
DIOWB#
55
DRDY#
49
SOE#
56
DREQA
45
DREQB
46
DDACK#A
47
DDACK#B
48
PWRGD
138
PCIRST#
3
RSTDRV
4
BCLK
14
OSC
6
cpu
O
SYSTEM MANAGEMENT INTERRUPT: SMI# is
asserted by the VT82C586 to CPU in response to
different Power-Management events.
cpu
O
NUMERICAL COPROCESSOR ERROR: This
signal is tied to the coprocessor error signal on the
CPU.
cpu
O
IGNORE ERROR: This pin is connected to the
ignore error pin on the CPU.
Enhanced IDE Interface
5v
O
DISK I/O READ A: Primary IDE channel drive
read strobe.
5v
O
DISK I/O WRITE A: Primary IDE channel drive
write strobe.
5v
O
DISK I/O READ B: Secondary IDE channel drive
read strobe.
5v
O
DISK I/O WRITE B: Secondary IDE channel drive
write strobe.
5v
I
I/O CHANNEL READY: IDE drive ready indicator.
5v
O
SYSTEM ADDRESS TRANSCEIVER OUTPUT
ENABLE: This signal controls the output enables of
the 245 transceivers that interface the DD[15:0]
signals to the SA[15:0]
5v
I
DISK DMA REQUEST A: Primary IDE channel
DMA request.
5v
I
DISK DMA REQUEST B: IDE channel DMA
request.
5v
O
DISK DMA ACKNOWLEDGE A: Primary IDE
channel DMA acknowledge.
5v
O
DISK DMA ACKNOWLEDGE B: Secondary IDE
channel DMA acknowledge.
This pin is used as power-up strap option:
Reset and Clock
5v
I
POWER GOOD: Connected to the POWERGOOD
signal on Power Supply.
pci
O
PCI RESET: An active low reset signal for the PCI
bus. The VT82C586 will generate PCIRST# during
the power-up or from the control register.
5v
O
RESET DRIVE: RSTDRV is the reset signal to the
ISA bus.
5v
O
BUS CLOCK: ISA bus clock
5v
I
OSCILLATOR: OSC is the 14.31818 Mhz clock
signal. It is used by the internal 8254
— 74 —
0/1: IDE fixed/relocatable I/O address
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