Application Restrictions - Omron CJ1W-CT021 Operation Manual

The following restrictions apply when using CJ1W-CT021 High-speed Counter Units.
When a 50-kHz noise filter is configured, External Control Inputs cannot read signals
shorter than 10 µs.
The time from signal input to resetting for External Control Inputs is 300 µs max.
The Open Gate Bit, Close Gate Bit, Preset Counter Bit, Reset Bit, or the Counter
Capture Bit in CIO may not be executed if turned ON for only one PLC-cycle. Always
keep these bits turned ON until the execution status changes in the corresponding
flag in n+24 or n+29.
External Control Inputs may not be reflected in the status of External Inputs (n+2,
n+5) if the pulse width is extremely short.
The following are the main reasons for this:
• The signal is shorter than the CPU Unit cycle time.
• The signal is shorter than the time the Data Transfer Busy bit is ON (e.g.,
during execution of an IOWR-instruction.)
The comparison operation stops for 1.5 ms from when the High-speed Counter Value
falls within the Upper Range Limit or Lower Range Limit for the Range Data.
However, the comparison does not stop for other counters.
Consider the time that the comparison is stopped when making settings for Range
Data.
When the High-speed Counter Value reaches the target value for Comparison Data,
comparison stops for 1.5 ms. However, comparison for other counters does not stop.
Consider the time the comparison stops when setting Comparison Data.
Comparison is stopped during the execution of IOWR/IORD-instructions and remains
stopped until the processing of the instruction has been completed. The Data
Transfer Busy bit is ON during this time.
This stopping of comparison during the execution of IOWR/IORD-instructions affects
counter comparisons for all counters.
Set Range Data and Comparison Data considering that comparisons are stopped by
execution of IOWR/IORD-instructions.
The measurement interval for the Pulse Rate Measurement Function normally varies
by 125 µs and can vary by a maximum of 1 ms. If the pulse rate value is averaged in
the ladder program, a value with a low (averaged) variation can be obtained.
The I/O Refresh will not occur while the Data Transfer Busy bit (CIO n+19, bit 02) is
ON, and the Counter Value will not be refreshed while this bit is ON.
The Unit's Data Transfer Busy bit (n+19, bit 02) will turn ON for approximately 120 ms
at restart and when the power is turned ON.
When using the IOWR-instruction to write Comparison Data to the Unit, check that
the target value being written will not be duplicated in the same Counter. If a target
value already set to the Unit is transferred, set the Comparison Data so that the same
value will be overwritten for the existing target value.
A CJ1-H or CJ1M CPU Unit is required to use external interrupt tasks. CJ1 CPU Units
do not support external interrupt tasks.
There are also restrictions on the position of the Unit on the Rack. Refer to the
section given in the right column for information on the restrictions.
Appendix D

Application Restrictions

Restriction Reference
1-3-3 "Input Specifications"
3-4 "Digital Input Functions"
3-4 "Digital Input Functions"
4-2 "Memory Allocation"
3-4 "Digital Input Functions"
3-5-1-2 "Configuration and operation
in Range Mode"
3-5-2-2 "Configuration and operation
in Comparison Mode"
3-5-1-2 "Configuration and operation
in Range Mode"
3-5-2-2 "Configuration and operation
in Comparison Mode"
3-7-2 "Rate Measurement"
4-1-1 "Basic Setup"
4-2-3 "CIO-Memory Mapping"
4-5 "Supported IOWR/IORD-
Instructions"
4-6 "Interrupts"
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