System Errors - Omron CJ1W-CT021 Operation Manual

Error codes
5-2-6

System Errors

Error Code 1 Error Code 2
000E 0000
0002 Time-Out in
milliseconds
Clearing System errors
The error indicates that the load of interrupts on the CJ-series CPU Unit is too
high. Clearing the error as mentioned before most probably needs additional
measures to be taken in order to prevent this error from happening in the future:
•
Mask one or more interrupts of the Unit, which caused the error.
•
Mask one or more interrupts of other Units in the system, which are generating
interrupts as well.
•
Reduce the execution time of the assigned External Interrupt Tasks.
External interrupt requests from the High-speed Counter Unit will not reach the
CPU Unit if the CPU Unit is not a CJ1-H or CJ1M CPU Unit (CJ1 CPU Units do not
support external interrupts), or the Unit is mounted at an incorrect position.
Be sure the High-speed Counter Unit is installed in the correct position. It must be
installed in one of the five positions immediately to the right of the CPU Unit (when
facing the PLC) if a CJ1-H CPU Unit is used, or in one of the three positions imme-
diately to the right of the CPU Unit if a CJ1M CPU Unit is used.
When errors occur in the CJ-series CPU Unit or on the I/O Bus the ERH-LED is
turned ON. At the occurrence of an I/O Bus error an error code (see n+17, n+18)
is generated as well.
Error
I/O Bus error
Time-Out error
Turn ON the power supply again or restart the system. If the error persists, then
replace the CJ-series CPU Unit.
Description
An error has occurred on the I/O Bus causing
the High-speed Counter Unit to be in an
undefined state. On occurrence of an I/O Bus
error you can configure the Outputs to keep
their last state or to have a predefined state
(refer to 3-5-4 "Output Control Configuration").
A cyclic refresh time-out error was generated
caused by a PLC system error or you have
chosen to disable the Cyclic Refresh of the
High-speed Counter Unit in the CJ-series PLC
settings. This error will be cleared as soon as
Cyclic Refresh will take place again. The IORF
ladder instruction has no influence on this
behaviour.
Section 5-2
141