Connection Between Cvic And Sdram - Sharp XG-V10WU Technical Manual

XG-V10WU
XG-V10WE

2. CONNECTION BETWEEN CVIC AND SDRAM

CVIC and SDRAM are connected in 128-bit data width as shown in the figure below.
CVIC
IC8025
The following signals coming out from CVIC are common for each SDRAM: CLK, XCS, XRAS, XCAS, XWE,
SD_BA0, SD_BA1, and SDA0 to SDA10.
The data bus (SDD0 ~ SDD127) is allocated to the four SDRAMs in every 32 bits.
Due to CVIC's internal data structure, DQM0 ~ DQM7 is allocated irregularly as shown in the figure below.
MSB
Byte 15 14
Bit
127-120 119-112 111-104 103-96
DQM DQM7
Pixel
32-bit access 127-96
CKE is tied to the high level (3.3V).
13 12 11 10
95-88 87-80
DQM6 DQM5
119-96 95-72
95-64
SDRAM
IC8319
IC8320
IC8321
IC8322
Figure 2-1.
9 8 7 6
79-72 71-64 63-56 55-48 47-40
DQM4 DQM3
71-48
63-32
Figure 2-2.
4
5 4 3 2 1
39-32 31-24 23-16 15-8
DQM2 DQM1 DQM0
47-24 23-0
31-0
LSB
0
7-0