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Pin Description - Sharp XG-V10WU Technical Manual

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XG-V10WU
XG-V10WE
Sync delay
Delays the sync signal for horizontal/vertical positioning of synchronization in the user menu.
Interrupt signal generation
Generates the interrupt signal for IX3434CE's internal use.
Auto sync adjustment
Automatically adjusts clock, horizontal phase, horizontal position and vertical position in the user menu synchroni-
zation on the basis of the received sync signal and data.

3-1-3. Pin description

Name
V0_ACT
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK
V0_PVDCLK/NVDCLK
V0_VDCLK_I
V0_RA
V0_GA
V0_BA
V0_RB
V0_GB
V0_BB
V1_ACT
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK
V1_PVDCLK/NVDCLK
V1_VDCLK_I
V1_RA
V1_GA
V1_BA
V1_RB
V1_GB
V1_BB
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_PADRST/NADRST
V0_PADCLK/NADCLK
V0_VDCLK_O
V0_CLP
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_PADRST/NADRST
V1_PADCLK/NADCLK
V1_VDCLK_O
V1_CLP
I/O
Bit Width
I
1
Tied GND
I
1
Data validity indicator signal
I
1
Horizontal sync signal
I
1
Vertical sync signal
I
1
Composite sync signal
I
1
Sync On Green signal
I
1
Horizontal sync signal synchronized with V0_VDCLKI
I
1
Tied GND
I
1
Tied GND
Clock for data
I
1
I
8
Input data R (Cr, Pr) (Single phase)
I
8
Input data G (Y) (Single phase)
I
8
Input data B (Cb, Pb) (Single phase)
I
8
Input data R (Cr, Pr) (Two phase)
I
8
Input data G (Y) (Two phase)
I
8
Input data B (Cb, Pb) (Two phase)
I
1
Tied GND
I
1
Tied GND
I
1
Horizontal sync signal
I
1
Vertical sync signal
I
1
Tied GND
I
1
Tied GND
I
1
Tied GND
I
1
Tied GND
I
1
Tied GND
I
1
4 x frequency clock from TLC2933 [TTL]
I
8
Input data R
I
8
Input data G
I
8
Input data B
I
8
Tied GND
I
8
Tied GND
I
8
Tied GND
O
1
Signal to stop external PLL phase comparison (Low-active)
O
1
OPEN
O
1
Horizontal sync signal for reference (Active low)
O
1
OPEN
O
1
OPEN
O
1
OPEN
O
1
Clamp pulse signal (Active high. Outputted from trailing edge of the horizontal sync pulse.)
O
1
Signal to stop external PLL phase comparison (Active high)
O
1
Horizontal sync signal for feedback (Active low)
* Used to control the dot clock frequency generated by external PLL.
O
1
Horizontal sync signal for reference (Active low)
O
1
OPEN
O
1
OPEN
O
1
External A/D converter operation clock [TTL]
O
1
Clamp pulse signal (Active high [1µs pulse width]. Outputted from leading edge
of the horizontal sync pulse.)
Description
latch [TTL]
14

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