Ix3434Ce (Input Section); Outline; Internal Block Diagram - Sharp XG-V10WU Technical Manual

3-1. IX3434CE (Input section)

3-1-1. Outline

Sync detect, clock control and data structure conversion are performed against the signals received.
Input lines consist of V0 and V1 lines. V1 lines are dedicated to the processing of component and composite signals of
480I/580I, while V0 lines are to the processing of signals with other resolutions.

3-1-2. Internal block diagram

V0_HSYNC, V0_VSYNC
V0_CSYNC, V0_GSYNC
V0_PDEN, V0_CLP
V0_HSYNR
V0_HSYNC2, V0_VAL
V0_RA0 ˜ 7, V0_GA0 ˜ 7
V0_BA0 ˜ 7
V0_RB0 ˜ 7, V0_GB0 ˜ 7
V0_BB0 ˜ 7
V0_VDCLK_I
V1_HSYNC, V1_VSYNC
V1_PDEN, V1_CLP
V1_HSYNR, V1_HSYNF
V1_RA0 ˜ 7, V1_GA0 ˜ 7
V1_BA0 ˜ 7
V1_VDCLK_I
V1_VDCLK_O
Sync detect
Checks the received sync signal to detect its resolution level.
Frequency divider
Generates the horizontal sync signal in accordance with the ratio of frequency division. (V1_HSYNF)
Clamp signal generation
Generates the clamp signal in accordance with the received sync signal.
Clock control
In V0 lines, the clock received at V0_VDCLK_I for 2-phase data is used also for data latching. In V1 lines, the 4 x
sampling clock frequency (V1_VDCLK_I) received from TLC2933 is divided to 1/4 to send it out from V1_VDCLK_O
and use it at TLC5733A.
Color space conversion
Data matrix conversion is performed.
Input section
V0 lines
Synchronization
Synchronization
Sync detect
Frequency
divider
Clamp signal
generation
Control signal
Data
Clock
control
V1 lines
Synchronization Synchronization
Sync detect
Frequency
divider
Clamp signal
generation
Control signal
Data
Clock
control
Figure 3-9.
Synchronization
Data processing
» Color space
conversion
» Sync delay
» Interrupt signal
generation
Clock
Synchronization
Data processing
» Color space
conversion
» Sync delay
» Interrupt signal
generation
Clock
13
XG-V10WU
XG-V10WE
HS_A, VS_A
Data
DATA_A
DE_A
HACT_A
VACT_A
PCLK_A
Auto sync
adjustment
HS_B, VS_B
Data
DATA_B
DE_B
HACT_B
VACT_B
PCLK_B