Sii151; Outline; Internal Block Diagram - Sharp XG-V10WU Technical Manual

3-3. SiI151

3-3-1. Outline

Receiver for DVI digital input.
Decodes TMDS analog signal and outputs pixel clock (ODCK), sync signal (HSYNC, VSYNC) synchronized with
clock, data enable (DE), and data (QE[23:0], QO[23:0]).

3-3-2. Internal block diagram

PIXS
DF0
OCK_INV
Termination
EXT_RES
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
PDO
STAG_OUT
ST
Control
Data Recovery
VCR
SYNC2
CH2
Data Recovery
VCR
SYNC1
CH1
Data Recovery
VCR
SYNC0
CH0
VCR PLL
Figure 3-17.
DATA
CTL3
SYNC2
CTL2
DATA
Channel Decoder
SYNC1 CTL1
SYNC
DATA
VSYNC
SYNC0
HSYNC
23
XG-V10WU
XG-V10WE
24
QE[23:0]
24
QO[23:0]
ODCK
DE
Panel
HSYNC
Interface
VSYNC
Logic
SCDT
CTL1
CTL2
CTL3