Main-Microprocessor Ic8001 (Ix3270Ce) Block Diagram - Sharp XG-V10WU Technical Manual

XG-V10WU
XG-V10WE

6-1-2. Main-microprocessor IC8001 (IX3270CE) block diagram

MLT
MMU
TLB
CCN
CACHE
[Code description]
ADC : A/D converter
BSC : Bus state controller 1
BSCP : Bus state controller 2
CACHE : Cache memory
CCN : Cache memory controller
CPG/WDT : Clock pulse generator/Watch-dog timer
CPU : Central processing unit
DAC : D/A converter
DMAC : Direct memory access controller
INTC : Interrupt controller
MLT : Multiplier
SH3
CPU
INTC
UBC
CPG/WDT
BSC
BSCP
DMAC
I/O port
External bus
interface
Figure 6-2.
52
RTC
TMU
SCI
IrDA
SCIF
ADC
DAC
MMU : Memory management unit
RTC : Real time clock
SCI : Serial communication interface
(With smart card interface)
IrDA : Serial communication interface
(With IrDA)
SCIF : Serial communication interface
(With FIFO)
TLB : Address conversion buffer
TMU : Timer unit
UBC : User break controller