Block Diagram - Sharp XG-V10WU Technical Manual

XG-V10WU
XG-V10WE

4-2. Block diagram

IX3399 Top
AI[13:1]
DIO[15:0]
WLNI
WHNI
RDNI
CSNI
CPUCLKI
RSI[9:0]
RTI[9:0]
20bit
CPU I/F
Horizontal keystone correction
Convergence adjustment
RAM
Color irregularity correction
LCD ex-display horizontal
gray mask control
20bit
RSO[9:0]
RTO[9:0]
Figure 4-6.
GSI[9:0] BSI[9:0]
GTI[9:0] BTI[9:0]
HI
Sync control
LCD panel
GSO[9:0] BSO[9:0]
GTO[9:0] BTO[9:0]
control signal
36
VI CLK2I
Timing
generator
DACLK2O
and
S/H-IC