Sharp XG-V10WU Technical Manual page 32

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XG-V10WU
XG-V10WE
V1_VDCLK_1 is processed to generate the sync signal with 4 x frequency to be outputted from V1_HSYNF.
V1_VDCLK_1 is given 1/4 frequency division in the clock control section and used as the sampling clock
(V1_VDCLK_0) of TLC5733A and also used as internal clock. External horizontal signal (VD_HSYNC) is given
sync detect and clamp generation to be outputted from V1_HSYNR. TL2933 performs phase comparison between
V1_HSYNF and V1_HSYNR to generate 4 x frequency clock via VCO. However, the phase comparison is not
performed during the period including the pulse width of external vertical sync signal (VD_VSYNC) as well as its
preceding and following 3 high levels, when V1_PDEN becomes high level.
V1_VDCLK_I
(VCO_OUT)
V1_HSYNR
(FIN_A)
V1_HSYNF
(FIN_B)
480I: 14.9[MHz]
525I: 15.0[MHz]
V1_VDCLK_O
(CLK)
V1_RA(AD1-8)
V1_GA(BD1-8)
V1_BA(CD1-8)
V1_CLP
(IC323 EN1)
V1_VSYNC
V1_PDEN
(PFD_INHIBIT)
The following shows the case of PinP.
Input
V1_VDCLK_I
480I
49.2 [MHz]
580I
58.6 [MHz]
* Clock control section performs 1/8 frequency division.
A0
A1
B0
B1
C0
C1
1[us]
3 line
6 line
Figure 3-29. V1 line timing chart
V1_VDCLK_O
6.15[MHz] (1/8 frequency division)
7.33 [MHz] (1/8 frequency division)
32
1/4 frequency division
A2
B2
C2
A3
B3
C3

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