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1. CVIC INTERNAL BLOCK DIAGRAM ........................... 2
2-1. SDRAM (HY57V653220B-TC7) ............................. 6
2-1-1. Description ...................................................... 6
2-1-2. Features .......................................................... 6
2-1-3. Pin layout ........................................................ 7
2-1-4. Pin description ................................................ 7
3-1. IX3434CE (Input section) ..................................... 13
3-1-1. Outline ........................................................... 13
3-1-2. Internal block diagram ................................... 13
3-1-3. Pin description .............................................. 14
3-2. CXA3516R ........................................................... 15
3-2-1. Outline ........................................................... 15
3-2-2. Internal block diagram ................................... 15
3-2-3. Pin layout ...................................................... 16
3-2-4. Pin description .............................................. 17
3-2-6. Timing chart when CXA3516R and
IX3434CE are connected .............................. 22
3-3. SiI151 ................................................................... 23
3-3-1. Outline ........................................................... 23
3-3-2. Internal block diagram ................................... 23
3-3-3. Pin layout ...................................................... 24
3-3-4. Pin description .............................................. 25
3-3-5. Timing ........................................................... 26
3-3-6. Power mode .................................................. 27
3-3-7. SiI151 timing chart ........................................ 27
3-4. TLC2933 .............................................................. 28
3-4-1. Outline ........................................................... 28
3-4-2. Internal block diagram ................................... 28
3-4-3. Pin layout ...................................................... 28
3-4-4. Pin description .............................................. 28
This Technical Manual is now prepared to help servicing the
LCD Projector equipped models, and its descriptions are lim-
ited only to "Description of New Circuit" etc.
For more understanding of each model, refer to its respective
Service Manual already issued.
(This Technical Manual is based on Models XG-V10WU and
XG-V10WE.)
TECHNICAL MANUAL
LCD PROJECTOR
XG-V10WU
XG-V10WE
CONTENTS
Page
3-5. TLC5733A ............................................................ 29
4-1. I/O waveform ........................................................ 34
4-2. Block diagram ...................................................... 36
4-3. Pin layout ............................................................. 38
4-4. Pin description ..................................................... 39
4-5. Color irregularity correction .................................. 42
5-1. D/A data I/O waveform ......................................... 47
5-2. D/A pin layout ....................................................... 47
5-3. D/A block diagram ................................................ 48
6. POWER CONTROL .................................................... 50
6-1. Description of Main-/Sub-microprcessor .............. 51
6-2. Data transmission system between
6-4. Key entry detection .............................................. 60
6-5. Detection of remote controller operation .............. 60
6-6. Temperature detection ......................................... 60
6-7. Detection of cooling fan rotation .......................... 61
6-8. Checking internal temperature and fan rotation all at once ..... 61
6-9. Appendix on power supply ................................... 61
1
3-5-1. Outline ........................................................... 29
3-5-2. Internal block diagram ................................... 29
3-5-3. Pin layout ...................................................... 29
3-5-4. Pin description .............................................. 30
3-5-5. Timing ........................................................... 31
3-5-6. V1 line system ............................................... 31
main-microprocessor and sub-microprocessor .... 55
XG-V10WU
XG-V10WE
TX0L1XG-V10WU
Page

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   Summary of Contents for Sharp XG-V10WU

  • Page 1: Lcd Projector, Sharp Corporation

    LCD Projector equipped models, and its descriptions are lim- ited only to “Description of New Circuit” etc. For more understanding of each model, refer to its respective Service Manual already issued. (This Technical Manual is based on Models XG-V10WU and XG-V10WE.) SHARP CORPORATION...

  • Page 2: Cvic Internal Block Diagram

    XG-V10WU XG-V10WE 1. CVIC INTERNAL BLOCK DIAGRAM Fig. 1 shows the data flow inside of the CVIC. External I/O Video Video input output Image Display Video processor output input module controller controller Internal bus External SDRAM controller controller External CPU, SDRAM etc.

  • Page 3

    XG-V10WU XG-V10WE Video input controller Video data entrance to CVIC, which performs the following processing. Conversion of the received video data into CVIC’s internal data structure. Storage of the converted video data into video buffer memory (SDRAM). Collecting data to detect resolution or refresh rate of the received video data.

  • Page 4: Connection Between Cvic And Sdram

    XG-V10WU XG-V10WE 2. CONNECTION BETWEEN CVIC AND SDRAM CVIC and SDRAM are connected in 128-bit data width as shown in the figure below. SDRAM CVIC IC8319 IC8025 IC8320 IC8321 IC8322 Figure 2-1. The following signals coming out from CVIC are common for each SDRAM: CLK, XCS, XRAS, XCAS, XWE, SD_BA0, SD_BA1, and SDA0 to SDA10.

  • Page 5

    XG-V10WU XG-V10WE The connection with each SDRAM is shown in the figures below. The numerals in each SDRAM box designate the pin numbers. Between CVIC and IC8319 Between CVIC and IC8321 CVIC SDRAM CVIC SDRAM IC8319 IC8321 IC8025 IC8025 XRAS...

  • Page 6: Sdram (hy57v653220b-tc7)

    XG-V10WU XG-V10WE 2-1. SDRAM (HY57V653220B-TC7) 2-1-1. Description The HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32. HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out- puts are synchronized with the rising edge of the clock input.

  • Page 7: Pin Layout

    XG-V10WU XG-V10WE 2-1-3. Pin layout DQ15 VDDQ VSSQ DQ14 DQ13 VSSQ VDDQ DQ12 DQ11 VDDQ VSSQ DQ10 VSSQ VDDQ DQM0 DQM1 /CAS /RAS 86pin TSOP II 400mil x 875mil 0.5mm pin pitch A10/AP DQM2 DQM3 DQ16 DQ31 VSSQ VDDQ DQ17...

  • Page 8: Input Wiring Diagram And Route Diagram

    XG-V10WU XG-V10WE 3. INPUT WIRING DIAGRAM AND ROUTE DIAGRAM » Wiring diagram IC8334, IC8335, IC8025 IC8336, IC8337 Noise filter, IX3434CE Peak clamp for Sync On Green IC8004 CX3516R IC8325 HOLD RA0 – RA7 P8012 G(Analog) EVEN/ODD GA0 – GA7 SYNCIN1 1C1 1Y BA0 –...

  • Page 9

    XG-V10WU XG-V10WE * V0 lines are connected to CXA3516R and SiI151, while V1 lines to TLC2933 and TLC5733A. » Route diagram (a) NTSC, PAL, 480I/580I IC8334, IC8335, component signal input IC8025 CVIC (VIC section) IC8336, IC8337 Noise filter, IX3434CE Peak clamp for...

  • Page 10

    XG-V10WU XG-V10WE (c) DVI analog signal input IC8334, IC8335, IC8025 CVIC (VIC section) IC8336, IC8337 Noise filter, IX3434CE Peak clamp for Sync On Green IC8004 CX3516R IC8325 HOLD RA0 – RA7 P8012 G(Analog) EVEN/ODD GA0 – GA7 SYNCIN1 1C1 1Y BA0 –...

  • Page 11

    XG-V10WU XG-V10WE (e) DTV (other than 480I/580I) IC8334, IC8335, IC8025 CVIC (VIC section) component signal input IC8336, IC8337 Noise filter, IX3434CE Peak clamp for Sync On Green IC8004 CX3516R IC8325 HOLD RA0 – RA7 P8012 G(Analog) EVEN/ODD GA0 – GA7...

  • Page 12

    XG-V10WU XG-V10WE (g) Other input (PC input, etc) than described above IC8334, IC8335, IC8025 CVIC (VIC section) (a)~(f) IC8336, IC8337 Noise filter, IX3434CE Peak clamp for Sync On Green IC8004 CX3516R IC8325 HOLD RA0 – RA7 P8012 G(Analog) EVEN/ODD GA0 – GA7...

  • Page 13: Ix3434ce (input Section)

    XG-V10WU XG-V10WE 3-1. IX3434CE (Input section) 3-1-1. Outline Sync detect, clock control and data structure conversion are performed against the signals received. Input lines consist of V0 and V1 lines. V1 lines are dedicated to the processing of component and composite signals of 480I/580I, while V0 lines are to the processing of signals with other resolutions.

  • Page 14: Pin Description

    XG-V10WU XG-V10WE Sync delay Delays the sync signal for horizontal/vertical positioning of synchronization in the user menu. Interrupt signal generation Generates the interrupt signal for IX3434CE’s internal use. Auto sync adjustment Automatically adjusts clock, horizontal phase, horizontal position and vertical position in the user menu synchroni- zation on the basis of the received sync signal and data.

  • Page 15: Selection Of Sync Signal Per Input

    XG-V10WU XG-V10WE 3-1-4. Selection of sync signal per input Sync signal is selected according to the input. IC8302 IC8325 INPUT Connect to Connect to Connect to V0_HSYNC V0_VSYNC SYNCIN1 DVI analog input DVI digital input 1C3(*1) 2C3(*1) Component/composite input of 480I/580I...

  • Page 16

    XG-V10WU XG-V10WE 3-2-3. Pin layout 108 107 105 104 103 102 101 100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 XCLKIN...

  • Page 17

    XG-V10WU XG-V10WE 3-2-4. Pin description Pin No. Name Standard Signal Description B/CbOUT 1.7V Amplifier output signal monitor ADDRESS – C slave address setting R/CrOUT 1.7V Amplifier output signal monitor – – No connection – – No connection XPOWER SAVE Power save setting DGNDREG –...

  • Page 18

    XG-V10WU XG-V10WE Pin No. Name Standard Signal Description SYNCIN1 Sync signal input 1 SYNCIN2 Sync signal input 2 CLPIN Clamp pulse input DVCCPLL – Digital power supply for PLL DGNDPLL – Digital ground for PLL AVCCVCO – Analog power supply for VCO of PLL AGNDVCO –...

  • Page 19: Outline Of Internal Function Blocks

    XG-V10WU XG-V10WE 3-2-5. Outline of internal function blocks » AMP block 3-channel amplifier optimizes, for ADC input, RGB analog input signal connected to condenser and YCbCr analog input signal. Analog input signal connected to condenser is given a sync clamp on its pedestal level by the clamp pulse received externally (CLPIN pin (113)).

  • Page 20

    XG-V10WU XG-V10WE In the case of RGB Sync On Green input, G/YIN1 pin (124) signal passes through the noise filter and the peak clamp circuit and goes into V0_GSYNC pin (316) of IX3434CE, same as DTV component input. IX3434CE (input section) carries out the mode detect and clamp generation to output G/YIN1 pin (124) at V0_CLP pin (128) where the signal is given a pedestal clamp.

  • Page 21

    XG-V10WU XG-V10WE » PLL block SYNCIN1 (In normal operation) SYNCIN2 (On DTV component input) G/YIN1 (On RGB Sync On Green input) Input of one of the above as sync signal Loop filter VCO frequency Phase Charge comparison divider pump (1, 1/2, 1/4, 1/8)

  • Page 22: Timing Chart When Cxa3516r And Ix3434ce Are Connected

    XG-V10WU XG-V10WE 3-2-6. Timing chart when CXA3516R and IX3434CE are connected V0_VDCLK_I (1/2CLK) V0_HSYNC2 (DSYNC) 500[ns] In normal operation V0_CLP (CLPIN) 600[ns] 500[ns] When 3 signals are synchronous in DTV (720I, 1080I, 1035I and 480P) V0_RA (RA0-RA7) V0_GA (GA0-GA7) V0_BA (BA0-BA7)

  • Page 23: Sii151

    XG-V10WU XG-V10WE 3-3. SiI151 3-3-1. Outline Receiver for DVI digital input. Decodes TMDS analog signal and outputs pixel clock (ODCK), sync signal (HSYNC, VSYNC) synchronized with clock, data enable (DE), and data (QE[23:0], QO[23:0]). 3-3-2. Internal block diagram PIXS OCK_INV...

  • Page 24

    XG-V10WU XG-V10WE 3-3-3. Pin layout CONTROLS EVEN 8-bits RED QE13 QE12 QE11 QE10 OVCC OGND OGND OVCC QO10 QO11 SiI151 QO12 100-Pin TQFP QO13 (Top View) QO14 QO15 SCDT QO16 STAG_OUT QO17 QO18 QO19 PIXS QO20 QO21 QO22 DIFFERNTIAL SIGNAL...

  • Page 25

    XG-V10WU XG-V10WE 3-3-4. Pin description Pin Name Description QE23-QE0 10-17, Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the first 24-bit pixel data for 2- 20-27, pixels/clock mode. Output data is synchronized with output data clock (ODCK).

  • Page 26: Timing

    XG-V10WU XG-V10WE 3-3-5. Timing Tccs Figure 3-19. Input timing of TMDS analog signal ODCK QE[23:0]/QO[23:0], DE, HSYNC, VSYNC, CTL[3:1] Figure 3-20. Output timing QE[23:0]/QO[23:0], DE, VSYNC, HSYNC, CTL[3:1], PLLCK Figure 3-21. Output timing in power down mode...

  • Page 27: Power Mode

    XG-V10WU XG-V10WE 3-3-6. Power mode Input Power ON/OFF CXA3516R SiI151 DVI analog DVI digital Input other than component/composite of 450I/580I CXA3516R POWER ON : XPOWERSAVE pin (6) is high. [Normal operation] POWER OFF : XPOWERSAVE pin (6) is low. [Power save mode] Output is Hi-Z.

  • Page 28: Tlc2933

    XG-V10WU XG-V10WE 3-4. TLC2933 3-4-1. Outline PLL for video (component/composite of 480I/580I) Phase comparison is made between FIN_A pin (4) and FIN_B pin (5) to output pixel clock (VCO_OUT) via VCO. 3-4-2. Internal block diagram VCO IN FIN-A Phase Voltage-...

  • Page 29: Tlc5733a

    XG-V10WU XG-V10WE 3-5. TLC5733A 3-5-1. Outline 3ch 8-bit A/D converter for video (component/composite of 480I/580I). Performs sampling of analog input according to CLK pin (56) to output the data. 3-5-2. Internal block diagram CLK A AD1-8 (Sampling RT A Output Data...

  • Page 30

    XG-V10WU XG-V10WE 3-5-4. Pin description Name Description Analog supply voltage of ADC A AAVCC Data output of ADC A (LSB: AD1, MSB:AD8) AD8-AD1 6-13 Analog input of ADC A Analog supply voltage of ADC B BAVCC Data output of ADC B (LSB: BD1, MSB:BD8)

  • Page 31

    XG-V10WU XG-V10WE 3-5-5. Timing tw(L) tw(H) tsu1 INIT OE A OE B OE C Analog Input Vt (ANLG) 6 fCLK Output Data A INVALID AD8-AD1 Output Data B INVALID B8-BD1 Output Data C INVALID CD8-CD1 = Input signal sampling point Figure 3-27.

  • Page 32

    XG-V10WU XG-V10WE V1_VDCLK_1 is processed to generate the sync signal with 4 x frequency to be outputted from V1_HSYNF. V1_VDCLK_1 is given 1/4 frequency division in the clock control section and used as the sampling clock (V1_VDCLK_0) of TLC5733A and also used as internal clock. External horizontal signal (VD_HSYNC) is given sync detect and clamp generation to be outputted from V1_HSYNR.

  • Page 33: Ix3399 Peripheral Ic Wiring Diagram

    XG-V10WU XG-V10WE 4. IX3399 PERIPHERAL IC WIRING DIAGRAM » Output data consists of 2 lines, the data S (even number pixel data 0, 2, 4...) and the data T (odd number pixel data 1, 3, 5...). » In the wiring diagram, input/output wiring of R and B data requires special attention.

  • Page 34: I/o Waveform

    XG-V10WU XG-V10WE 4-1. I/O waveform [CPU bus timing chart] CPUCLKI AI[13:1] CSNI WLHI WHNI RDNI DIO[15:1] (Input) DIO[15:1] (Output) Figure 4-2. [Input data timing chart] Approx. 18ns 54MHz Clock (Input) CLK2I Data S (Input) RSI[9:0], GSI[9:0], BSI[9:0] Data T (Input)

  • Page 35

    XG-V10WU XG-V10WE [Horizontal sync timing chart] HSync HSync HFrontPorch HBack Data (*) H Data Enable RSI [9:0], RTI [9:0], GSI [9:0], GTI[9:0], 1clk = 1CLKI = Approx. 18ns BSI [9:0], BTI [9:0] HSync = 56 clk HBackPorch = 148 clk...

  • Page 36: Block Diagram

    XG-V10WU XG-V10WE 4-2. Block diagram RSI[9:0] GSI[9:0] BSI[9:0] RTI[9:0] GTI[9:0] BTI[9:0] CLK2I 20bit IX3399 Top CPU I/F AI[13:1] DIO[15:0] Horizontal keystone correction Sync control WLNI WHNI RDNI CSNI CPUCLKI Convergence adjustment Color irregularity correction LCD ex-display horizontal Timing gray mask control...

  • Page 37

    XG-V10WU XG-V10WE Horizontal keystone correction Horizontal keystone correction is performed as illustrated in the figure below. (Vertical keystone correction is done in the preceding CVIC.) Before correction After correction Figure 4-7. Convergence adjustment By delaying the video signal in a single pixel unit individually for RGB, the horizontal display position can be relo- cated in the reverse direction of convergence deviation.

  • Page 38

    XG-V10WU XG-V10WE 4-3. Pin layout Figure 4-9.

  • Page 39

    XG-V10WU XG-V10WE 4-4. Pin description Pin layout Location Pin Name Description Location Pin Name Description *GND – – *OVDD – – BTO9 OUT Output B video data (Data T) RTO3 OUT Output R video data (Data T) BTO6 OUT Output B video data (Data T)

  • Page 40

    XG-V10WU XG-V10WE Location Pin Name Description Location Pin Name Description ENBX1BO OUT PRGRO OUT S/H start LCD H clock 1 control or DESO[]output HSTBO OUT LCD H start PRGGO OUT S/H start VSTBO OUT D-S/H control pin (Note 4) *OVDD –...

  • Page 41

    XG-V10WU XG-V10WE Location Pin Name Description Location Pin Name Description *IVDD – – PLL_TESTI IC function test pin (Tied 0) RTI9 Input R video data (Data T) PLL_VCOIN VCO control voltage input from BTI5 Input R video data (Data T)

  • Page 42: Color Irregularity Correction

    XG-V10WU XG-V10WE 4-5. Color irregularity correction [What is color irregularity?] The phenomenon that color reproduction differs depending on the points on the screen of three-panel LCD projec- tor. It is conspicuous especially when displaying all white, all black or all gray screen.

  • Page 43

    XG-V10WU XG-V10WE [Principle of color irregularity correction] The color irregularity occurs when optical output against video signal input does not meet the expected value due to the above mentioned factors 1 to 4. For its correction, therefore, it works to apply the correction voltage on a line preceding the LCD panel so that the optical output against the signal input can meet the expected value.

  • Page 44

    XG-V10WU XG-V10WE 2. Color irregularity correction data making tool (Application program for Windows) The color irregularity correction data making tool is similar to the above described color irregularity correction data making system but with its camera replaced by human eyes. With this tool, the operator will observe the screen with eyes, judge the state of color irregularity, and adjust the correction data with the tool so that the luminance on the screen becomes even.

  • Page 45

    XG-V10WU XG-V10WE [Processor of color irregularity correction] In the projector, the correction data will be added to the video signal at the following two parts before sending the signals to LCD panel. 1. Color irregularity correction IC (Digital processing) 2. Color irregularity NOKO correction circuit (Analog processing)

  • Page 46: D/a Peripheral Ic Wiring Diagram

    XG-V10WU XG-V10WE 5. D/A PERIPHERAL IC WIRING DIAGRAM » D/A consists of 2 lines of data, the data S (even number pixel data 0, 2, 4...) and the data T (odd number pixel data 1, 3, 5...). » In the wiring diagram, input/output wiring of R and B data requires special attention.

  • Page 47: D/a Data I/o Waveform

    XG-V10WU XG-V10WE 5-1. D/A data I/O waveform Approx. 18ns 54MHz Clock RCLK, GCLK, BCLK Input data R9 R0, G9 G0, B9 B0 100% Output data RO, GO, BO Figure 5-2. 5-2. D/A pin layout VREF B0 (LSB) G9 (MSB) Digital Analog Figure 5-3.

  • Page 48: D/a Block Diagram

    XG-V10WU XG-V10WE 5-3. D/A block diagram (LSB) R0 4LSB S CURRENT CELLS 6LSB S LATCHES CURRENT DECODER CELLS DECODER CLOCK GENERATOR (MSB) R9 (LSB) G0 4LSB S CURRENT CELLS 6LSB S LATCHES CURRENT DECODER CELLS DECODER CLOCK GENERATOR (MSB) G9...

  • Page 49: D/a Pin Description And I/o Pin Equivalent Circuit

    XG-V10WU XG-V10WE 5-4. D/A pin description and I/O pin equivalent circuit Code Equivalent circuit Description 1~10 R0~R9 Digital input Pin (1) R0 (LSB) ~ Pin (10) R9 (MSB) 11~20 G0~G9 Pin (11) G0 (LSB) ~ Pin (20) G9 (MSB) Pin (21) B0 (LSB) ~ Pin (30) B9 (MSB)

  • Page 50: Power Control

    XG-V10WU XG-V10WE 6. POWER CONTROL The set performs power ON/OFF control with the built-in two microprocessor. The role of each microprocessor is as follows. 1 Sub-microprocessor IC2601 (IX3502CE) OUTPUT UNIT Decoding the main unit key entry and the remote controller signals, Control of data communication with PC via RS232C, Peripheral power control for the main microprocessor.

  • Page 51: Main-microprocessor Ic8001 (ix3270ce) Pin Layout

    XG-V10WU XG-V10WE 6-1. Description of Main-/Sub-microprocessor 6-1-1. Main-microprocessor IC8001 (IX3270CE) pin layout EXTAL XTAL VCC(RTC) XTAL2 EXTAL2 VSS(RTC) PTH[6] VCC[PLL2] iRQ0/iRL0/PTH[0] CAP2 iRQ1/iRL1/PTH[1] VSS[PLL2] iRQ2/iRL2/PTH[2] VSS[PLL1] iRQ3/iRL3/P TH[3] CAP1 iRQ4/PTH[4] VCC[PLL1] D31PTB[7] D30PTB[6] PTF[0] PINT8 D29PTB[5] PTF[1] PINT9 D28PTB[4] PTF[2] PINT10...

  • Page 52: Main-microprocessor Ic8001 (ix3270ce) Block Diagram

    XG-V10WU XG-V10WE 6-1-2. Main-microprocessor IC8001 (IX3270CE) block diagram INTC CPG/WDT CACHE IrDA BSCP SCIF DMAC I/O port External bus interface [Code description] : A/D converter : Memory management unit : Bus state controller 1 : Real time clock BSCP : Bus state controller 2...

  • Page 53: Sub-microprocessor Ic2601 (ix3502ce) Pin Layout

    XG-V10WU XG-V10WE 6-1-3. Sub-microprocessor IC2601 (IX3502CE) pin layout P46/INT26/UT2 P47/INT27/ADST P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 (Top view) P56/AN6 P57/AN7 P60/INT10 P61/INT11 P62/INT12 Figure 6-3.

  • Page 54: Sub-microprocessor Ic2601 (ix3502ce) Block Diagram

    XG-V10WU XG-V10WE 6-1-4. Sub-microprocessor IC2601 (IX3502CE) block diagram Sub-clock Energy-saving CMOS I/O port P63/INT13/X0A generator circuit P00/P07 (32.768kHz) P64/X1A Clock control P10/P17 P60/INT10 ˜ Clock pre-scaler P62/INT12 CMOS I/O port External interrupt 1 (Edge) 12-bit PPG01 P20/PMIX CMOS I/O port...

  • Page 55: Data Transmission System Between Main-microprocessor And Sub-microprocessor

    XG-V10WU XG-V10WE 6-2. Data transmission system between main-microprocessor and sub-microprocessor Data transmission system Synchronized data transmission system 8-bit/data construction Transmission speed 230.6kbps Sync clock is sent out from the sub-microprocessor IC2601. Signal line SCK0 : Sync clock (Sent out from the sub-microprocessor)

  • Page 56

    XG-V10WU XG-V10WE Data format Normal data transmission system : Data (18-byte) transmission/Response (2-byte) reception (Constant regardless of the way of transmission) Special data transmission system : No restriction on data volume. No response received. (Regardless of the way of transmission)

  • Page 57

    XG-V10WU XG-V10WE Normal data transmission between main and sub-microprocessor Clock/data relations SCK0 TXD0 (RXD0) Data loading point Example of the data "A5" From main to sub (On power supply, etc) SCK0 TXD0 (Insignificant data) Transmission data (18-byte) RXD0 Response data...

  • Page 58

    2. Transmission of gamma correction data 3. Transmission of color irregularity correction data (In servicing) In performing 1 and 2 above, the Sharp Advanced Presentation Software Professional Edition (SAPSPro), which comes with the projector, is required. In the special data transmission system, the sub-microprocessor will operate as follows.

  • Page 59

    XG-V10WU XG-V10WE Special data transmission between main and sub-microprocessor Switching to special data transmission system Normal data transmission system Special data transmission system (Example of transmission from main to sub) SCK0 (Notify entry to special data transmission system) TXD0 Transmission data (18byte)

  • Page 60: Simple Check Of Rs-232c Out Port

    XG-V10WU XG-V10WE 6-3. Simple check of RS-232C OUT port 1 Supply the return code (0x0D) to the port. 2 If “RETRY” or the returned code comes back in text, the port and the sub-microprocessor IC2601 are working. 6-4. Key entry detection The operation of the key (QSW-Z0524CEZZ) is detected by the sub-microprocessor IC2601 (IX3502CE).

  • Page 61: Detection Of Cooling Fan Rotation

    XG-V10WU XG-V10WE 6-7. Detection of cooling fan rotation Rotational speeds of the cooling fans used in the set are detected. Sequence of detection 1. Pulse signal sent out from each fan, which is variable with rotational speed, is supplied to IC7301 at its pins (6) (IC0), (5) (IC1), (4) (IC2), and (3) (IC3).

  • Page 62

    XG-V10WU XG-V10WE Table of I C bus slave address [1] SCL1 line (3.3V) IC Code Slave Address (Hexadecimal) 1 IC4302 CXA1839 (Component) 2 IC8003 AT24C128N (E PROM) 3 IC7601 LM81 (Fan monitor) 4 IC7402 CXA1875 (Serial DAC1) 40/41 5 IC7302...

  • Page 63

    XG-V10WU XG-V10WE Extension I/O pin setting C bus SCL2 line Signal Name Setting Remarks SELA SELA/SELB=LL: Video, LH: RGB Sync signal switch SELB HL: DVI Analog, HH: DVI Digital IC8299 SELPCH L: CSYNC used, H: H/VSYNC used I/O-1 (Tied L)

  • Page 64

    XG-V10WU XG-V10WE Function Spec Remarks L: OFF, H: ON Segment LED (Digit of 10) L: OFF, H: ON Segment LED (Digit of 10) IC5604 L: OFF, H: ON Segment LED (Digit of 10) I/O-6 L: OFF, H: ON Segment LED (Digit of 10) L;...

  • Page 65

    XG-V10WU XG-V10WE Port C Pin Name Signal Name Remarks PTC[0]/PINT[0] RLED2 (Undefined) PTC[1]/PINT[1] (Undefined) SCL2 line I C data output PTC[2]/PINT[2] SCL2 OUT SCL2 line I C clock PTC[3]/PINT[3] SLTDO C data output for extension slot (SLTCK line) PTC[4]/PINT[4] SLTCK...

  • Page 66

    XG-V10WU XG-V10WE Port H Pin Name Signal Name Remarks IRQO/PTH[0] C1 INT Other CVIC (IC8025) interrupt input IRQ1/PTH[1] IR INT (Unused) IRQ2/PTH[2] (Unused) IRQ3/PTH[3] (Unused) Other IRQ4/PTH[4] (Unused) Other PTH[5]/ADTRG (Unused) PTH[6] (Unused) TCLK/PTH[7] (Unused) Port J Pin Name Signal Name...

  • Page 67

    XG-V10WU XG-V10WE DAC pin setting DAC1(OUTPUT UNIT) IC5201 Pin No. Code Name Function VPRG [Process]PSIG voltage during PRG period G3GAIN [Process]G2GAIN fine tuning (Spare) R1BLK [Process]R1-BLK G1BLK [Process]G1-BLK B1BLK [Process]B1-BLK R1GAIN [Process]R1-GAIN G1GAIN [Process]G1-GAIN B1GAIN [Process]B1-GAIN VRCOM [Process]VRCOM VGCOM [Process]VGCOM...

  • Page 68

    XG-V10WU XG-V10WE COPYRIGHT © 2000 BY SHARP CORPORATION ALL RIGHTS RESERVED. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher.

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