Timing; V1 Line System - Sharp XG-V10WU Technical Manual

3-5-5. Timing

tw(H)
CLK
INIT
OE A
OE B
OE C
Analog
Input Vt (ANLG)
Output Data A
AD8-AD1
Output Data B
B8-BD1
Output Data C
CD8-CD1
= Input signal sampling point

3-5-6. V1 line system

Clamp
VD_RGB
circuit
EN1
tw(L)
0 1 2 3 4
tsu1
n+3
n+4
n+2
n
n+1
6 fCLK
INVALID
INVALID
INVALID
Figure 3-27. Data output timing (format2)
TLC5733A[TI]
AIN AD1-8
BIN BD1-8
CIN CD1-8
CLK
VD_HSYNC
VD_VSYNC
TL2933[TI]
VCO_OUT
FIN_A
FIN_B
PFD_INHIBIT
Sampling clock for AD
480I:14.9[MHz]
525I:15.0[MHz]
Figure 3-28. V1 line system schematics
5 6 7 8 9
n+5
n+7
n+6
tpd
A0 A1 A2
tpd
B0 B1 B2
tpd
C0 C1 C2
(VIC section)
V1_RA[8]
V1_GA[8]
V1_BA[8]
» Clock control
(1/4 frequency
division)
V1_HSYNC
» Sync detect
V1_VSYNC
» Frequency divider
4 x frequency clock
480I:59.6[MHz]
525I:60.1[MHz]
V1_VDCLK_I[TTL]
V1_VDCLK_O[TTL]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
31
XG-V10WU
XG-V10WE
10 11 12
A3 A4 A5 A6 A7
B3 B4 B5 B6 B7
C3 C4 C5 C6 C7
Data
Sync signal
Internal clock