Input Wiring Diagram And Route Diagram - Sharp XG-V10WU Technical Manual

XG-V10WU
XG-V10WE

3. INPUT WIRING DIAGRAM AND ROUTE DIAGRAM

» Wiring diagram
P8012
G(Analog)
R(Analog)
G(Analog)
B(Analog)
R(Video)
G(Video)
B(Video)
IC8302
1C0
1C1
IH_CON
1C2
1C3
2C0
2C1
IV_CON
2C2
2C3
CSYNC
DVI_RO
DVI_GO
DVI_BO
IC8331
IC8330
VH_IN
VV_IN
IX3434CE (Input section)
Sync detect, clock control, color space conversion, data structure conversion, and auto sync adjustment.
CXA3516R
3ch 8-bit 165MSPS A/D converter with built-in amplifier and PLL.
SiI151
Receiver for DVI digital input
TLC2933
PLL for V1 lines
TLC5733A
3ch 8-bit A/D converter (for component/composite signals of 480I/580I)
Noise filter,
Peak clamp for
Sync On Green
CX3516R
IC8325
HOLD
RA0 – RA7
EVEN/ODD
GA0 – GA7
1C0
SYNCIN1
1C1 1Y BA0 – BA7
SYNCIN2
RB0 – RB7
CLPIN
GB0 – GB7
G/YIN1
BB0 – BB7
B/CbIN1
R/CrIN1
G/YIN2
DSYNC/DIVOUT
B/CbIN2
R/CrIN2
1Y
2Y
SiI151
RX2+
C1 2
1 RX2-
C2
QE23-QE0
RX1+
10
C3
QO23-QO0
RX1-
9
RX0+
18
C4
RX0-
6 3 17
23 RXC+
RXC-
24
8
6 3
P8001
IC8323,
IC8324,
IC8326
TLC5733A
AIN
Clamp
BIN
circuit
CIN
CLK
EN1
IC8334, IC8335,
IC8336, IC8337
IC8004
1/2CLK
IC8298
ODCK
DE
HSYNC
VSYNC
IC8328
TLC2933
VCO_OUT
FIN_A
FIN_B
PFD_INHIBIT
IC8000
AD1-8
BD1-8
CD1-8
Figure 3-1.
8
IC8025
IX3434CE
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_ACT
V0_VAL V0 lines
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_ACT
V1 lines
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_PVDCLK/NVDCLK[ECL]
V1_VDCLK_I[TTL]
V1_VDCLK_O[TTL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP