Pin Description - Sharp XG-V10WU Technical Manual

4-4. Pin description

Pin layout
Location Pin Name I/O
A1 *GND –
A2 BTO9 OUT Output B video data (Data T)
A3 BTO6 OUT Output B video data (Data T)
A4 BTO2 OUT Output B video data (Data T)
A5 BTO0 OUT Output B video data (Data T)
A6 GTO7 OUT Output G video data (Data T)
A7 GTO3 OUT Output G video data (Data T)
A8 GTO0 OUT Output G video data (Data T)
A9 RTO8 OUT Output R video data (Data T)
A10 RTO6 OUT Output R video data (Data T)
A11 RTO4 OUT Output R video data (Data T)
A12 RTO1 OUT Output R video data (Data T)
A13 *GND –
A14 RSO1 OUT Output R video data (Data S)
A15 RSO2 OUT Output R video data (Data S)
A16 DACLK1O OUT
A17 RSO7 OUT Output R video data (Data S)
A18 GSO0 OUT Output G video data (Data S)
A19 *OVDD –
A20 GSO1 OUT Output G video data (Data S)
B1 HSTGO OUT LCD H start
B2 LCLKNO OUT
B3 BTO7 OUT Output B video data (Data T)
B4 BTO3 OUT Output B video data (Data T)
B5 BTO1 OUT Output B video data (Data T)
B6 GTO8 OUT Output G video data (Data T)
B7 GTO4 OUT Output G video data (Data T)
B8 GTO1 OUT Output G video data (Data T)
B9 RTO9 OUT Output R video data (Data T)
B10 RTO7 OUT Output R video data (Data T)
B11 RTO5 OUT Output R video data (Data T)
B12 RTO2 OUT Output R video data (Data T)
B13 RSO0 OUT Output R video data (Data S)
B14 *OVDD –
B15 *GND –
B16 RSO5 OUT Output R video data (Data S)
B17 RSO8 OUT Output R video data (Data S)
B18 GSO2 OUT Output G video data (Data S)
B19 *OVDD –
B20 *GND –
C1 VSTGO OUT LCD V start
C2 LCLKPO OUT
C3 BTO8 OUT Output B video data (Data T)
C4 BTO4 OUT Output B video data (Data T)
C5 *OVDD –
C6 GTO9 OUT Output G video data (Data T)
C7 GTO5 OUT Output G video data (Data T)
C8 GTO2 OUT Output G video data (Data T)
C9 *OVDD –
C10 *OVDD –
Description
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Single phase output sync clock for D/A drive
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PECL differential output for S/H-IC drive
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PECL differential output for S/H-IC drive
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Location Pin Name I/O
C11 *OVDD –
C12 RTO3 OUT Output R video data (Data T)
C13 RTO0 OUT Output R video data (Data T)
C14 *OVDD –
C15 RSO3 OUT Output R video data (Data S)
C16 RSO6 OUT Output R video data (Data S)
C17 RSO9 OUT Output R video data (Data S)
C18 GSO3 OUT Output G video data (Data S)
C19 GSO4 OUT Output G video data (Data S)
C20 GSO5 OUT Output G video data (Data S)
D1 *CVDD –
D2 HSTRO OUT LCD H start
D3 *GND –
D4 BTO5 OUT Output B video data (Data T)
D5 *GND –
D6 *OVDD –
D7 GTO6 OUT Output G video data (Data T)
D8 *OVDD –
D9 *GND –
D10 *GND –
D11 *CVDD –
D12 *CVDD –
D13 *GND –
D14 *GND –
D15 RSO4 OUT Output R video data (Data S)
D16 *GND –
D17 GSO6 OUT Output G video data (Data S)
D18 *OVDD –
D19 GSO7 OUT Output G video data (Data S)
D20 GSO8 OUT Output G video data (Data S)
E1 *OVDD –
E2 VSTRO OUT LCD V start
E3 *GND –
E4 *GND –
E5 *OVDD –
E6 *GND –
E7 *GND –
E8 *GND –
E9 *GND –
E11 *OVDD –
E12 *GND –
E13 DACLK2O OUT
E14 *CVDD –
E15 *GND –
E16 *GND –
E17 GSO9 OUT Output G video data (Data S)
E18 BSO0 OUT Output B video data (Data S)
E19 BSO1 OUT Output B video data (Data S)
E20 BSO2 OUT Output B video data (Data S)
F1 VCKRO OUT LCD V clock
39
XG-V10WU
XG-V10WE
Description
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Two phase output sync clock for D/A drive
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