Sharp XG-V10WU Technical Manual page 9

* V0 lines are connected to CXA3516R and SiI151, while V1 lines to TLC2933 and TLC5733A.
» Route diagram
(a) NTSC, PAL, 480I/580I
component signal input
P8012
R(Analog)
G(Analog)
B(Analog)
R(Video)
G(Video)
B(Video)
IH_CON
IV_CON
CSYNC
R(VIDEO)
G(VIDEO)
B(VIDEO)
(b) DVI digital signal input
R(Analog)
G(Analog)
B(Analog)
R(VIDEO)
G(VIDEO)
B(VIDEO)
Noise filter,
Peak clamp for
Sync On Green
CX3516R
IC8325
HOLD
G(Analog) EVEN/ODD
1C0
SYNCIN1
1C1 1Y
SYNCIN2
CLPIN
G/YIN1
B/CbIN1
R/CrIN1
G/YIN2
B/CbIN2
R/CrIN2
IC8302
1C0
1C1
1Y
1C2
1C3
2C0
2C1
2C2 2Y
2C3
Sil151
DVI_RO
RX2+
C1 2
DVI_GO
1 RX2-
C2
DVI_BO
10 RX1+
C3
9 RX1-
IC8331
18 RX0+
C4
RX0-
6 3 17
RXC+
23
RXC-
IC8330 24
8
6 3
P8001
VH_IN
VV_IN
IC8323,
IC8324,
IC8326
AIN
Clamp
BIN
circuit
CIN
CLK
EN1
Figure 3-2.
Noise filter,
Peak clamp for
Sync On Green
CX3516R
IC8325
HOLD
P8012
EVEN/ODD
G(Analog)
1C0
SYNCIN1
1C1 1Y
SYNCIN2
CLPIN
G/YIN1
B/CbIN1
R/CrIN1
G/YIN2
B/CbIN2
R/CrIN2
IC8302
1C0
1C1
IH_CON
1C2 1Y
1C3
2C0
2C1
IV_CON
2Y
2C2
2C3
CSYNC
Sil151
DVI_RO
RX2+
C1 2
DVI_GO
RX2-
1
C2
DVI_BO
10 RX1+
C3
RX1-
9
IC8331
RX0+
18
C4
6 3 17 RX0-
23 RXC+
24 RXC-
IC8330
8
6 3
P8001
VH_IN
VV_IN
IC8323,
IC8324,
IC8326
AIN
Clamp
BIN
circuit
CIN
CLK
EN1
Figure 3-3.
IC8334, IC8335,
IC8336, IC8337
IC8004
RA0 – RA7
GA0 – GA7
BA0 – BA7
RB0 – RB7
GB0 – GB7
BB0 – BB7
1/2CLK
DSYNC/DIVOUT
IC8298
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
IC8328
TLC2933
VCO_OUT
FIN_A
FIN_B
PFD_INHIBIT
IC8000
TLC5733A
AD1-8
BD1-8
CD1-8
IC8334, IC8335,
IC8336, IC8337
IC8004
RA0 – RA7
GA0 – GA7
BA0 – BA7
RB0 – RB7
GB0 – GB7
BB0 – BB7
1/2CLK
DSYNC/DIVOUT
IC8298
QE23-QE0
QO23-QO0
ODCK
DE
HSYNC
VSYNC
IC8328
TLC2933
VCO_OUT
FIN_A
FIN_B
PFD_INHIBIT
IC8000
TLC5733A
AD1-8
BD1-8
CD1-8
9
XG-V10WU
XG-V10WE
IC8025 CVIC (VIC section)
IX3434CE
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_ACT
V0_VAL V0 lines
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_ACT
V1 lines
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_PVDCLK/NVDCLK[ECL]
V1_VDCLK_I[TTL]
V1_VDCLK_O[TTL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP
IC8025 CVIC (VIC section)
IX3434CE
V0_RA[8]
V0_GA[8]
V0_BA[8]
V0_RB[8]
V0_GB[8]
V0_BB[8]
V0_ACT
V0_VAL V0 lines
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_PVCLK/NVCLK[ECL]
V0_PVDCLK/NVDCLK[ECL]
V0_VDCLK_I[TTL]
V0_VDCLK_O[TTL]
V0_PADCLK/NADCLK[ECL]
V0_PADRST/NADRST[ECL]
V0_PDEN
V0_HSYNF
V0_HSYNR
V0_CLP
V1_RA[8]
V1_GA[8]
V1_BA[8]
V1_RB[8]
V1_GB[8]
V1_BB[8]
V1_ACT
V1 lines
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_PVCLK/NVCLK[ECL]
V1_PVDCLK/NVDCLK[ECL]
V1_VDCLK_I[TTL]
V1_VDCLK_O[TTL]
V1_PADCLK/NADCLK[ECL]
V1_PADRST/NADRST[ECL]
V1_PDEN
V1_HSYNF
V1_HSYNR
V1_CLP