Clock Inputs Display - HP 16550A User Reference

The Format Menu

Clock Inputs Display

Clock Inputs Display
Beneath the Clock Inputs display, and next to the bit reference line, is a
display of all clock inputs available in the present configuration. In a one card
module the J and K clocks appears with pod pair 1/2, the L and M with pod
pair 3/4, and clocks N and P with pod pairs 5/6. In a two card module the
next six clocks appear to the left of the displayed master clocks, and are used
as data channels. With the exception of the Range resource, all unused clock
bits can be used as data channels. If any clock line is used as a data channel,
the bit must be assigned. Activity indicators above the clock identifier show
clock or data signal activity.
Clock inputs display
Clocks assigned
as data channels
Clock Inputs Display
4–13