HP 16550A User Reference page 59

100-mhz state/500-mhz timing logic analyzer
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All combinations of the J, K, and L clock and Q1 and Q2 qualifiers are ORed
to the clock combinations of the M, N, and P clocks and Q3 and Q4 qualifiers.
Clock edges are ORed to clock edges, clock qualifier are ANDed to clock
edges, and clock qualifiers can be either ANDed or ORed together.
The clock threshold level is the same as the level assigned in the Pod
Threshold field.
Clock edge
selection menu
Clock Edges and Levels
The Format Menu
Master and Slave Clock Field (State only)
4–21

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