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General Information
Key Features
Key Features
•
100-MHz state and 500-MHz timing acquisition speed.
•
96 data/6 clock channels, expandable to 198 data/6 clock channels.
•
Lightweight passive probes for easy hookup and compatibility with
previous HP logic analyzers and preprocessors.
•
Variable setup/hold time, 3.5 ns window.
•
External arming to/from other modules through the intermodule bus.
•
4 Kbytes deep memory on all channels with 8 Kbytes in half channel
modes.
•
Marker measurements.
•
12 levels of trigger sequencing for state and 10 levels of sequential
triggering for Timing.
•
Both state and timing analyzers can use 10 pattern resource terms, two
range terms, and two timer/counters to qualify and trigger on data. The
timing analyzer also has two edge terms available.
•
Predefined trigger macros for easy configuration of trigger specifications.
•
100-MHz time and number-of-states tagging.
•
Full programmability.
•
Mixed State/Timing and State/State (interleaved) display.
•
Compare, Chart, and Waveform displays.
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