Master And Slave Clock Field (State Only) - HP 16550A User Reference

The Format Menu

Master and Slave Clock Field (State only)

Master and Slave Clock Field (State only)
The Master and Slave Clock fields are used to construct a clocking
arrangement. A clocking arrangement is the assignment of appropriate
clocks, clock edges, and clock qualifier levels which allow the analyzer to
synchronize itself on valid data.
Clock Selections
When the Master or Slave Clock field is selected, a clock/qualifier selection
menu appears showing the available clocks and qualifiers for a clocking
arrangement. There are up to six clocks available (J through P), and four
clock qualifiers available (Q1 through Q4).
Each pod cable has one clock line and at least one clock edge must be
assigned for all pods in a state analyzer. If a second analyzer card is
connected, the lower card in the frame becomes the master and only its six
clocks can be assigned as clocks. The remaining unassigned clocks can be
used as data channels.
See Also
The "Pod Clock Field" found earlier in this chapter for information on
selecting clocking arrangement types such as Master, Slave, or Demultiplex.
Master clock field
Master Clock Field
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