HP 16550A User Reference page 241

100-mhz state/500-mhz timing logic analyzer
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Specifications
The specifications are the performance standards against which the product
is tested.
Maximum State Speed
Minimum State Clock Pulse Width
Minimum Master to Master Clock Time
Minimum Glitch Width
Threshold Accuracy
1
Setup/Hold Time
:
Single Clock, Single Edge
Single Clock, Multiple Edges
Multiple Clocks, Multiple Edges
1 Specified for an input signal VH = -0.9 V, VL = -1.7 V, slew rate = 1 V/ns, and threshold = -1.3 V.
Specifications and Characteristics
100 MHz
1
3.5 ns
1
10.0 ns
3.5 ns
± (100 mV + 3% of threshold setting)
0/3.5 ns through 3.5/0 ns,
adjustable in 500 ps increments
0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500 ps intervals
0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500 ps increments
Specifications
12–3

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