HP 16550A User Reference page 47

100-mhz state/500-mhz timing logic analyzer
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The Format Menu
Timing Acquisition Mode Field (Timing only)
Transitional Half Channel 250 MHz Mode
The total memory depth is 8 Kbytes with a channel width of 17 channels on
one pod. The pod used within the pod pair is selectable. Data is sampled for
new transitions every 4 ns.
Transitional timing running at 250 MHz is the same as the 125 MHz mode,
except that two single-pod data samples (17 bits x 2 = 34 bits) are stored
instead of one full-pod pair data sample (34 bits). This is because in half
channel mode, data is multiplexed into the sequencer pipeline in two 17-bit
samples. The first 17 bit sample is latched, the next 17-bit sample is sent
down the pipeline along with the latched 17-bit sample.
This operation keeps the pipeline frequency down to 125 MHz. It should be
noted that the transition detector still looks at a full 34 bits. This means it is
looking at two samples at a time instead of one. In this mode, between 682
and 4094 transitions are stored.
Minimum Transitions Stored The following example shows what data
is stored from a data stream with transitions that occur at a slow rate
(more than 24 ns apart).
Minimum Transitions Stored
4–9

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