Characteristics - HP 16550A User Reference

100-mhz state/500-mhz timing logic analyzer
Hide thumbs Also See for 16550A:
Table of Contents

Advertisement

Specifications and Characteristics

Characteristics

Characteristics
The characteristics are not specifications, but are included as additional
information.
Maximum State Clock Rate
Maximum Conventional Timing Rate
Maximum Transitional Timing Rate
Maximum Timing with Glitch Rate
2
Channel Count
Memory Depth
Supplemental Characteristics
Probes
Input Resistance
Input Capacitance
Minimum Voltage Swing
Threshold Range
Maximum Probe Input Voltage
State Analysis
State/Clock Qualifiers
3
Time Tag Resolution
Maximum Time Count Between States
Maximum State Tag Count
2Channel count is doubled when two HP 16550A cards are connected together.
3Maximum state clock rate with time or state tags on is 100 MHz. When all pods are assigned to a state or
timing machine, time or state tags halve the memory depth.
12–4
Full Channel Half Channel
100 MHz
250 MHz
125 MHz
N/A
102/204
4K
100 KΩ, ± 2%
~ 8 pF
500 mV, peak-to-peak
± 6.0 V, adjustable in 50 mV
increments
± 40 volts peak, CAT I.
6
8 ns
34 seconds
3
4.29 x 10
100 MHz
500 MHz
250 MHz
125 MHz
51/102
8K
9

Advertisement

Table of Contents
loading

Table of Contents