Siemens CPU 948 Programming Manual page 145

SIM/LIM – set/read interrupt
condition code mask (UAMW)
15
INTX INTE INTF INTG WEFE
15
– KB KDB STS
CPU 948 Programming Guide
C79000-G8576-C848-04
The interrupt mask "masks" interrupts in the interrupt condition code
word until the end of the cycle, i.e. all interrupts remain pending, but
the program is not interrupted by them.
Bit in the interrupt condition code mask = 0: interrupt disabled
Bit in the interrupt condition code mask = 1: interrupt enabled
Meaning of the bits in UAMW-H or ACCU-1-H:
8 7
WA PA BULE
Meaning of the bits in UAMW-L or ACCU-1-L:
8 7
TLAF SUF STUEB STUEU NAU
Table 3-28 Meaning of the abbreviations in UAMW
Abbrev. Meaning
INTX S5 bus/system interrupt A, B, C or D (slot-
dependent)
INTE S5 bus/system interrupt E
INTF S5 bus/system interrupt F
INTG S5 bus/system interrupt G
WEFE Collision of timed interrupts
WA Timed interrupt
PA Process interrupt
BULE Bus lock error
PEU I/Os not ready
HALT Stop instruction from coordinator COR
ES Single step mode
AV Address comparison active
INTAS Interrupt from SPU processor
TAU Clock failure of SPU processor
DARY Continuous ready (access to faulty memory)
KZU Bracket counter overflow
PEU HALT ES AV
ZA QVZ ADF
High word
Executive Operations
0
INTAS TAU DARY KZU
0
PARE ZYK STOP HOLD
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