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Programming Examples in the STL, LAD and CSF Methods of Representation
Logic operations
(continued)
Scan for signal state "0"
Logical/circuit diagram
I 1.5
I 1.6
I 1.5
I 1.6
&
Q 3.0
Q 3.0
Output Q 3.0 is "1" only when input I 1.5 has signal state "1"
(normally open contact activated) and input I 1.6 has signal
state "0" (normally closed contact activated)
Set/reset operations
RS flip-flop for a latching signal output
Logical/circuit diagram
I 1.4
I 2.7
I 1.4
R
S
1 1
1 0
Q 3.5
Signal state "1" at input I 2.7 sets the flip-flop
(signal state "1" at output Q 3.5).
If the signal state at input I 2.7 changes to "0", the
state of output Q 3.5 is retained (i.e. the signal is latched).
Signal state "1" at input I 1.4 resets the flip-flop
(signal state "0" at output Q 3.5).
If the signal state at input I 1.4 changes to "0", the
state of Q 3.5 is retained.
When the set signal (input I 2.7) and the reset signal
(input I 1.4) are applied at the same time, the scan
operation programmed last (in this case AI 1.4)
remains in effect for the rest of the program (reset priority).
CPU 948 Programming Guide
C79000-G8576-C848-04
Statement
list
A
I 1.5
AN I 1.6
=
Q3.0
Statement
list
A
I 2.7
S
Q 3.5
I 2.7
A
I 1.4
R
Q 3.5
Q 3.5
STEP 5 representation
Ladder
diagram
I 1.5
I 1.6
Q 3.0
STEP 5 representation
Ladder
diagram
I 2.7
Q3.5
S
I 1.4
R
Q
Control system
flowchart
I 1.5
&
I 1.6
Q 3.0
Control system
flowchart
Q3.5
I 2.7
S
I 1.4
R
Q
3 - 37
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