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Programming Examples in the STL, LAD and CSF Methods of Representation
Logic operations
(continued)
OR-before-AND operation
Logical/circuit diagram
I 6.0 I 6.1 I 6.2 I 6.3
I 6.0
1
&
1
Q 2.1
Q 2.1
Output Q 2.1 is "1" when input I 6.0 or input I 6.1 and one
of the inputs I 6.2 or I 6.3 has signal state "1"
Output Q 2.1 is "0" when input I 6.0 has signal state "0"
and the AND condition is not satisfied
OR-before-AND operation
Logical/circuit diagram
I 1.4 I 1.5
I 2.0 I 2.1
1
1
&
Q 3.0
Output Q 3.0 is "1" when both OR conditions are satisifed
Output Q 3.0 is "0" when at least one OR condition is not satisfied
3 - 36
/1st example
Statement
list
I 6.0
A
I 6.2
I 6.3
O
I 6.1
A
A (
I 6.1
O
I 6.2
O
I 6.3
)
=
Q2.1
/2nd example
Statement
list
A (
I 1.4
O
O
I 1.5
I 1.4
I 1.5
)
I 2..0
I 2.1
A (
O
I 2.0
Q3.0
O
I 2.1
)
=
Q3.0
STEP 5 representation
Ladder
diagram
I 6.0
Q 2.1
I 6.2
I 6.1
I 6.3
STEP 5 representation
Ladder diagram
I 1.4
I 2..0
Q 3.0
I 1.5
I 2.1
Control system
flowchart
I 6.0
1
I 6.1
&
I 6.3
1
I 6.2
Q 2.1
Control system
flowchart
I 1.4
1
I 1.5
&
I 2.0
1
I 2.1
Q 3.0
CPU 948 Programming Guide
C79000-G8576-C848-04
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