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Programming Examples in the STL, LAD and CSF Methods of Representation
Set/reset operations
(continued)
Simulation of a momentary contact relay (one shot)
Logical/circuit diagram
I 1.7
I 1.7
F4.0
F2.0
I 1.7
F 4.0
F 2.0
On each leading edge of the signal at input I 1.7,
the AND condition (AI 1.7 and AN F 4.0) is satisfied;
the RLO is "1". This sets flags F 4.0 (edge flag) and
F 2.0 (pulse flag).
In the next processing cycle, the AND condition
AI 1.7 and AN F 4.0 is not satisfied, since flag F 4.0
has already been set.
Flag F 2.0 is reset.
Flag F 2.0 therefore only remains "1" for one program
run.
Binary scaler (binary divider)
Logical/circuit diagram
I 1.0
I 1.0
M1.0
M1.1
F 2.0
Q 3.0
0
I 1.0
Q 3.0
The binary scaler (output Q 3.2) changes its state
each time input I 1.0 changes its signal state from 0
to 1 (leading edge). Therefore, only half the input
frequency appears at the output of the memory cell.
CPU 948 Programming Guide
C79000-G8576-C848-04
Statement
list
A
I 1.7
AN
F 4.0
=
F 2.0
F2.0
A
F 2.0
S
F 4.0
AN
I 1.7
R
F 4.0
Statement
list
A
I 1.0
AN
F 1.0
=
F 1.1
A
F 1.1
S
F 1.0
AN
I 1.0
Q3.0
R
F 1.0
A
F 1.1
A
Q3.0
=
F 2.0
A
F 1.1
AN
Q3.0
AN
F 2.0
S
Q 3.0
A
F 2.0
R
Q 3.0
STEP 5 representation
Ladder
diagram
F 2.0
I 1.7 F 4.0
F 4.0
F 2.0
S
I 1.7
R
Q
STEP 5 representation
Ladder
diagram
I1.0
F1.0
F1.1
F1.1
F1.0
S
I1.0
R
Q
F1.1 Q3.0
F 2.0
F1.1 Q3.0 F2.0
Q3.0
S
F2.0
R
Q
Control system
flowchart
I 1.7
&
F 4.0
F 2.0
F 4.0
F 2.0
S
I 1.7
R
Q
Control system
flowchart
I1.0
&
F1.1
F1.0
F1.0
S
F1.1
I1.0
R Q
F1.1
&
Q3.0
F2.0
F1.1
&
Q3.0
Q3.0
S
F2.0
F2.0
R
Q
3 - 39
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