Download  Print this page

Advertisement

Hardware Information
8.3

Hardware Address Table

In the distribution of the address areas a distinction is made between
S Memory address area and
S I/O address area.
Different read/write signals (I/O WR, I/O RD, MEMR, MEMR) are used to
reference these areas. The following tables will give you an overview of the
address areas used. Please refer to the descriptions of the individual functional
groups for more details.
Functional Principle of the Memory Decoding
The Pentium II CPU has a memory address area of 64 Gbytes, of which 4GBytes
can be used. The CPU has 64 data lines, 33 address lines and 8 byte lines
(BE0 ... BE7), which encode the unavailable address lines A0, A1 and A2.
The CPU address bus is mapped via the PAC (System Controller) on the PCI
address bus. The memory addresses of addresses 0000 0000h to 0009 FFFFh
(640kByte) and addresses 0010 0000h to 2FFF FFFFh (768MByte) are excluded
here.
The ISA bridge PIIX (PCI ISA IDE Xcellerator) precisely maps the ISA address bus
once on the PCI address bus. The ISA address bus for 8 bit modules includes the
address area from A0 to A19, which corresponds to the CPU addresses
0000 0000h to 000F FFFFh (1MByte).
For 16Bit ISA modules, the address bus is expanded by the address lines
A20...A23, and therefore addresses 0000 0000h to 00FF FFFFh (16MByte). The
distinction between the 1MByte and the 16MByte ISA address area is made by
special Memory–Read/Write signals, which are only activated if the address lines
A20, A21, A22 and A23 have a logical zero level.
If address ranges which are occupied by the main memory or PCI bus are
addressed by the CPU, no ISA bus control signals are generated, i.e. an ISA bus
unit is not addressed in these memory areas. Conversely, an ISA busmaster
cannot reach addresses above 16MByte. In order to obtain a larger address area
for dual-port RAM expansions than the memory address area between 640kByte
and 1MByte, various decoding holes are provided in the Pentium PU basic board:
S The CPU address area FFF0 0000h to FFFD FFFFh (1024k–128 k BIOS =
896 kByte) is mapped in the ISA address area 00F0 0000h to 00FD FFFFh and
is always addressed in the CPU address area. The decoding of the address
lines A24 to A31 missing on the ISA bus is effected by special hardware on the
basic board.
S The CPU address area 00F0 0000 to 00FF FFFF is mapped in the
ISA address area 00F0 0000 to 00FF FFFF (16 MByte memory window).
This setting can be toggled on or off in setup.
8-4
SIMATIC Box PC 620 Manual
C79000-G7076-C639-04

Advertisement

   Also See for Siemens SIMATIC Box PC 620

Comments to this Manuals

Symbols: 0
Latest comments: