Revision History - Xilinx AC701 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
10/23/2012 1.0 Initial Xilinx release.
01/30/2013 1.1 Updated photograph in
Figure
under
paragraph under
paragraphs under
Express Edge Connector, page
Revised third and fourth rows in
Revised second paragraph and added fourth paragraph under
page
Figure 1-34, page 52
AC701 Board Power System, page 66
Added third paragraph under
Revised
Added
08/28/2013 1.2 Added
Table
Master Constraints File
AC701 Evaluation Board
Figure 1-2, page 10
1-3. Revised last paragraph under
USB JTAG Module, page
U3 IN0: 125 MHz Clock Generator, page
U3/U4 IN2: FMC HPC GBT Clocks, page
37, and the first paragraph under
46. Revised first paragraph under
and Figure 1-35, page
Power Management, page
Figure A-2, page 80. Updated the
Appendix G, Regulatory and Compliance
Figure 1-10. Revised Figure
1-18, and Table 1-26. Updated
Listing.
www.xilinx.com
Revision
to revision 1.0 of the AC701 board. Revised
DDR3 Memory Module, page
22, third paragraph under
Table 1-13, page 39 and the fifth row in
I2C Bus Switch, page
53. Revised Figure 1-41, page
and section XADC Power System Measurement, page
61. Revised
Master Constraints File Listing in Appendix
Information.
1-2, Figure 1-49, and Figure
Monitoring Voltage and
14, fourth paragraph
GTP Transceivers, page 34, first
32, first, second and third
34, fourth paragraph under
SFP/SFP+ Connector, page
Table 1-14, page
LCD Character Display,
48. Added Figure 1-32, page
56. Added section
Figure 1-49, page
1-50. Updated Table 1-1,
Current. Updated Appendix C,
UG952 (v1.3) April 7, 2015
PCI
38.
39.
52,
71.
77.
C.