Xilinx AC701 User Manual page 90

Appendix C: Master Constraints File Listing
90
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set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN N7
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN K3
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN H1
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN M6
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN K1
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN M7
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN K5
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN L4
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN J1
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN J3
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN M4
set_property IOSTANDARD SSTL15
#DDR3 BA
set_property PACKAGE_PIN H2
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN M1
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN N1
set_property IOSTANDARD SSTL15
#USB UART
set_property PACKAGE_PIN T19
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
set_property PACKAGE_PIN U19
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
set_property PACKAGE_PIN V19
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
set_property PACKAGE_PIN W19
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
#IIC
set_property PACKAGE_PIN N18
set_property IOSTANDARD LVCMOS33 [get_ports IIC_SCL_MAIN]
set_property PACKAGE_PIN K25
set_property IOSTANDARD LVCMOS33 [get_ports IIC_SDA_MAIN]
set_property PACKAGE_PIN R17
set_property IOSTANDARD LVCMOS33 [get_ports IIC_MUX_RESET_B]
#PCIE
set_property PACKAGE_PIN K26
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_WAKE_B]
set_property PACKAGE_PIN M20
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST]
set_property PACKAGE_PIN F11
set_property IOSTANDARD LVDS_25
set_property PACKAGE_PIN E11
set_property IOSTANDARD LVDS_25
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[get_ports DDR3_A11]
[get_ports DDR3_A10]
[get_ports DDR3_A10]
[get_ports DDR3_A9]
[get_ports DDR3_A9]
[get_ports DDR3_A8]
[get_ports DDR3_A8]
[get_ports DDR3_A7]
[get_ports DDR3_A7]
[get_ports DDR3_A6]
[get_ports DDR3_A6]
[get_ports DDR3_A5]
[get_ports DDR3_A5]
[get_ports DDR3_A4]
[get_ports DDR3_A4]
[get_ports DDR3_A3]
[get_ports DDR3_A3]
[get_ports DDR3_A2]
[get_ports DDR3_A2]
[get_ports DDR3_A1]
[get_ports DDR3_A1]
[get_ports DDR3_A0]
[get_ports DDR3_A0]
[get_ports DDR3_BA2]
[get_ports DDR3_BA2]
[get_ports DDR3_BA1]
[get_ports DDR3_BA1]
[get_ports DDR3_BA0]
[get_ports DDR3_BA0]
[get_ports USB_UART_TX]
[get_ports USB_UART_RX]
[get_ports USB_UART_RTS]
[get_ports USB_UART_CTS]
[get_ports IIC_SCL_MAIN]
[get_ports IIC_SDA_MAIN]
[get_ports IIC_MUX_RESET_B]
[get_ports PCIE_WAKE_B]
[get_ports PCIE_PERST]
[get_ports PCIE_CLK_QO_P]
[get_ports PCIE_CLK_QO_P]
[get_ports PCIE_CLK_QO_N]
[get_ports PCIE_CLK_QO_N]
AC701 Evaluation Board
UG952 (v1.3) April 7, 2015