Xilinx AC701 User Manual page 86

Appendix C: Master Constraints File Listing
86
Send Feedback
set_property PACKAGE_PIN D23
set_property IOSTANDARD LVDS_25
set_property PACKAGE_PIN D24
set_property IOSTANDARD LVDS_25
#EMCCLK
set_property PACKAGE_PIN P16
set_property IOSTANDARD LVCMOS33 [get_ports FPGA_EMCCLK]
#DDR3
#CONTROL
set_property PACKAGE_PIN P4
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN N4
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN R1
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN P1
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN T4
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN T3
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN T2
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN R2
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN U2
set_property IOSTANDARD SSTL15
set_property PACKAGE_PIN N8
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
set_property PACKAGE_PIN U1
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]
#DDR3 CLKs
set_property PACKAGE_PIN M2
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN L2
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN N3
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN N2
set_property IOSTANDARD DIFF_SSTL15
#DDR3 DQS
set_property PACKAGE_PIN H7
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN G7
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN J4
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN H4
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN B5
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN A5
set_property IOSTANDARD DIFF_SSTL15
set_property PACKAGE_PIN C1
set_property IOSTANDARD DIFF_SSTL15
www.xilinx.com
[get_ports REC_CLOCK_C_P]
[get_ports REC_CLOCK_C_P]
[get_ports REC_CLOCK_C_N]
[get_ports REC_CLOCK_C_N]
[get_ports FPGA_EMCCLK]
[get_ports DDR3_CKE0]
[get_ports DDR3_CKE0]
[get_ports DDR3_CKE1]
[get_ports DDR3_CKE1]
[get_ports DDR3_WE_B]
[get_ports DDR3_WE_B]
[get_ports DDR3_RAS_B]
[get_ports DDR3_RAS_B]
[get_ports DDR3_CAS_B]
[get_ports DDR3_CAS_B]
[get_ports DDR3_S0_B]
[get_ports DDR3_S0_B]
[get_ports DDR3_S1_B]
[get_ports DDR3_S1_B]
[get_ports DDR3_ODT0]
[get_ports DDR3_ODT0]
[get_ports DDR3_ODT1]
[get_ports DDR3_ODT1]
[get_ports DDR3_RESET_B]
[get_ports DDR3_TEMP_EVENT]
[get_ports DDR3_CLK0_P]
[get_ports DDR3_CLK0_P]
[get_ports DDR3_CLK0_N]
[get_ports DDR3_CLK0_N]
[get_ports DDR3_CLK1_P]
[get_ports DDR3_CLK1_P]
[get_ports DDR3_CLK1_N]
[get_ports DDR3_CLK1_N]
[get_ports DDR3_DQS7_P]
[get_ports DDR3_DQS7_P]
[get_ports DDR3_DQS7_N]
[get_ports DDR3_DQS7_N]
[get_ports DDR3_DQS6_P]
[get_ports DDR3_DQS6_P]
[get_ports DDR3_DQS6_N]
[get_ports DDR3_DQS6_N]
[get_ports DDR3_DQS5_P]
[get_ports DDR3_DQS5_P]
[get_ports DDR3_DQS5_N]
[get_ports DDR3_DQS5_N]
[get_ports DDR3_DQS4_P]
[get_ports DDR3_DQS4_P]
AC701 Evaluation Board
UG952 (v1.3) April 7, 2015