Yamaha TF5 Service Manual page 91

CS5368-CQZR (X8488A00) ADC (Analog to Digital Converter)
PIN
NAME I/O
NO.
1 AIN2+ I Differential Analog– Audio signals are
2 AIN2- I presented differently to the delta sigma
modulators via the AIN+/- pins.
3 GND I Ground– Ground reference. Must be
connected to analog ground.
4 VA I Analog Power– Positive power supply for
the analog section
5 REF_GND I Reference Ground– For the internal sampling
circuits. Must be connected to analog ground.
6 FILT+ O Positive Voltage Reference– Reference
voltage for internal sampling circuits.
7 VQ O Quiescent Voltage– Filter connection for
the internal quiescent reference voltage.
8 GND I Ground– Ground reference. Must be
connected to analog ground.
9 VA I Analog Power– Positive power supply for
the analog section
10 GND I Ground– Ground reference. Must be
connected to analog ground.
11 AIN4+ I
12 AIN4- I
13 AIN3+ I
Differential Analog– Audio signals are
14 AIN3- I
presented differently to the delta sigma
15 AIN7+ I
modulators via the AIN+/- pins.
16 AIN7- I
17 AIN8+ I
18 AIN8- I
19 GND I Ground– Ground reference. Must be
connected to analog ground.
20 VX I Crystal Oscillator Power– Also powers control
logic to enable or disable oscillator circuits.
21 XTI I/O Crystal Oscillator Connections– I/O pins
22 XTO I/O for an external crystal which may be used
to generate MCLK.
23 MCLK I/O System Master Clock– When a crystal is
used, this pin acts as a buffered MCLK
Source (Output). When the oscillator function
is not used, this pin acts as an input for the
system master clock. In this case, the XTI
and XTO pins must be tied low.
AK4396VF-E2 (X8324A00) DAC (Digital to Analog Converter)
PIN
NAME I/O
NO.
1 DV - Digital ground
SS
2 DV - Digital power supply +3.3 V
DD
3 MCLK I Master clock input
4 PDN I Power-down mode
5 BICK I Audio serial data clock
6 SDATA I Audio serial data input
7 LRCK I L/R clock
SMUTE/CSN
8 I Soft mute/Chip select
9 DFS0/CAD0 I Sampling speed mode select/Chip address 0
10 DEM0/CCLK I De-emphasis enable 0/Control data clock
11 DEM1/CDTI I De-emphasis enable 1/Control data input
12 DIF0 I
13 DIF1 I Digital input format
14 DIF2 I
PIN
FUNCTION
NO.
FUNCTION
NAME I/O
24 LRCK/FS I/O Serial Audio Channel Clock– In I
Serial Audio Channel Select. When low, the
odd channels are selected.
In LJ Mode, Serial Audio Channel Select.
When high, the odd channels are selected.
In TDM Mode, a frame sync signal. When
high, it marks the beginning of a new frame
of serial audio samples. In Slave Mode, this
pin acts as an input pin.
25 SCLK I/O Main timing clock for the Serial Audio Interface–
During Master Mode, this pin acts as an output,
and during Slave Mode it acts as an input pin.
26 SDOUT4 O Serial Audio Data– Channels 7,8.
27 SDOUT2 O Serial Audio Data– Channels 3,4.
28 VLS I Serial Audio Interface Power– Positive
power for the serial audio interface.
29 GND I Ground– Ground reference. Must be
connected to analog ground.
30 SDOUT1 O Serial Audio Data– Channels 1,2.
31 SDOUT3 O Serial Audio Data– Channels 5,6.
32 GND I Ground– Ground reference. Must be
connected to analog ground.
33 VD I Digital Power– Positive power supply for
the digital section.
34 CLKMODE I CLKMODE– Setting this pin HIGH places
a divide-by-1.5 circuit in the MCLK path to
the core device circuitry.
35 VLC I Control Port Interface Power– Positive
power for the control port interface.
36 OVFL O Overflow– Detects an overflow condition
on both left and right channels.
37 DIF1 I DIF1, DIF0– Inputs of the audio interface
38 DIF0 I format.
39 M1 I Mode Selection– Determines the
40 M0 I operational mode of the device.
41 RST I Reset– The device enters a low power
mode when low.
42 MDIV I MCLK Divider– Setting this pin HIGH
places a divide-by-2 circuit in the MCLK
path to the core device circuitry.
43 AIN6+ I
44 AIN6- I
Differential Analog– Audio signals are
45 AIN5+ I
presented differently to the delta sigma
46 AIN5- I
modulators via the AIN+/- pins.
47 AIN1+ I
48 AIN1- I
PIN
NAME I/O
NO.
15 TTL I CMOS/TTL level select
16 VREFL I Low level voltage reference input
17 VREFH I High level voltage reference input
18 AV - Analog power supply +5 V
DD
19 AV - Analog ground
SS
20 AOUTR- O Rch negative analog output
21 AOUTR+ O Rch positive analog output
22 AOUTL- O Lch negative analog output
23 AOUTL+ O Lch positive analog output
24 VCOM O Common voltage output
25 P/S I Parallel/serial select
26 TST1/DZFL O Test 1/Lch zero input detect
27 TST2/CAD1 I Test 2/Chip address 1
28 ACKS/DZFR I/O Master clock auto setting mode/Rch zero input detect
TF5/TF3/TF1
HAAD (HACOM): IC903
FUNCTION
2
S Mode,
DA1 (DACOM): IC901
FUNCTION
91