Yamaha TF5 Service Manual page 102

TF5/TF3/TF1
TPS65910AA1RS (YF900A00) POWER MANAGEMENT IC
PIN
NAME I/O
NO.
1 PWRHOLD I Switch-on/-off control signal
2 VMMC O LDO regulator output
3 VCC3 I VMMC VAUX33 power input
4 VAUX33 O LDO regulator output, VDD3 internal
regulated supply
5 VDIG2 O LDO regulator output
6 VCC6 I VDIG1, VDIG2 power input
7 VDIG1 O LDO regulator output
8 SDA/SDI I/O I2C bidirectional data signal/serial peripheral
interface data input (multiplexed)
9 SCL/SCK I/O I2C bidirectional clock signal/serial peripheral
interface Clock Input (multiplexed)
10 SDASR/EN2 I/O I2C SmartReflex bidirectional data signal/
enable of supplies (multiplexed)
11 SCLSR/EN1 I/O I2C SmartReflex bidirectional clock signal/
enable of supplies (multiplexed)
12 VDDIO I Digital I/Os supply
13 VCCIO I VIO DC-DC power input
14 SWIO O VIO DC-DC switched output
15 GNDIO I/O VIO DC-DC power ground
16 VFBIO I VIO feedback voltage
17 REFGND I/O Reference ground
18 VREF O Bandgap voltage
19 BOOT1 I Power-up sequence selection
20 OSC32KIN I 32-kHz crystal oscillator
21 OSC32KOUT I 32-kHz crystal oscillator
22 VDAC O LDO regulator output
23 VCC5 I VDAC, VPLL power input
LAN8720A-CP-TR (YF905A00) ETHERNET TRANSCEIVER (PHY)
PIN
NAME I/O
NO.
1 VDD2A - +3.3V Analog Port Power to Channel 2 and
the internal regulator.
2 LED2/ I/O Link Speed LED Indication./This configuration
nINTSEL strap selects the mode of the nINT/REFCLKO pin.
3 LED1/ I/O Link activity LED Indication./This configuration
REGOFF strap is used to disable the internal 1.2V regulator.
4 XTAL2 O External crystal output.
5 XTAL1/ I External crystal input./Single-ended clock
CLKIN oscillator input.
6 VDDCR - Supplied by the on-chip regulator unless
configured for regulator off mode via the
REGOFF configuration strap.
7 RXD1/ I/O Bit 1 of the 2 data bits that are sent by the
MODE1 transceiver on the receive path./Combined
with MODE0 and MODE2, this configuration
strap sets the default PHY mode.
8 RXD0/ I/O Bit 0 of the 2 data bits that are sent by the
MODE0 transceiver on the receive path./Combined
with MODE1 and MODE2, this configuration
strap sets the default PHY mode.
9 VDDIO - +1.6V to +3.6V variable I/O power.
10 RXER/ I/O This signal is asserted to indicate that
PHYAD0 an error was detected somewhere in the
frame presently being transferred from the
transceiver./This configuration strap sets the
transceiver's SMI address.
102
PIN
FUNCTION
NO.
PIN
FUNCTION
NO.
NAME I/O
24 VPLL O LDO regulator output
25 TESTV O Analog test output (DFT)
26 BOOT0 I Power-up sequence selection
27 VBACKUP I Backup battery input (short to VCC5 if not used)
28 VCC7 I VRTC power input, VDD3 internal and analog
references supply
29 VRTC O LDO regulator output
30 VFB3 I VDD3 feedback voltage
31 SW3 O VDD3 DC-DC switched output
32 VFB1 I VDD1 feedback voltage
33 PWRON I External switch-on control (ON button)
34 GND1 I/O VDD1 DC-DC power ground
35 SW1 O VDD1 DC-DC switched output
36 VCC1 I VDD1 DC-DC power input
37 SLEEP I Active-sleep state transition control signal
38 CLK32KOUT O 32-kHz clock output
39 GPIO/CKSYNC I/O Configurable general-purpose I/O or DC-DCs
synchronization clock input signal
40 NRESPWRON O Power off reset
41 VCC2 I VDD2 DC-DC power input
42 SW2 O VDD2 DC-DC switched output
43 GND2 I/O VDD2 DC-DC power ground
44 VFB2 I VDD2 DC-DC feedback voltage
45 INT1 O Interrupt flag
46 VAUX1 O LDO regulator output
47 VCC4 I VAUX1, VAUX2 power input
48 VAUX2 O LDO regulator output
49 GNDP - Ground
NAME I/O
11 CRS_DV/ I/O This signal is asserted to indicate the receive
MODE2 medium is non-idle./Combined with MODE0
and MODE1, this configuration strap sets the
default PHY mode.
12 MDIO I/O Serial Management Interface data input/
output.
13 MDC I Serial Management Interface clock.
14 nINT/ O Active low interrupt output./This optional
REFCLKO 50MHz clock output is derived from the
25MHz crystal oscillator.
15 nRST I System reset.
16 TXEN I Indicates that valid transmission data is
present on TXD[1:0].
17 TXD0 I The MAC transmits data to the transceiver
using this signal.
18 TXD1 I The MAC transmits data to the transceiver
using this signal.
19 VDD1A - +3.3V Analog Port Power to Channel 1.
20 TXN I/O Transmit/Receive Negative Channel 1.
21 TXP I/O Transmit/Receive Positive Channel 1.
22 RXN I/O Transmit/Receive Negative Channel 2.
23 RXP I/O Transmit/Receive Positive Channel 2.
24 RBIAS I This pin requires connection of a 12.1k ohm
(1%) resistor to ground.
25 VSS - Common ground.
MAIN (MAINCOM): IC903
FUNCTION
MAIN (MAINCOM): IC915
FUNCTION