ST STM32F31xx User Manual page 341

UM1581
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#define: RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
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#define: RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
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#define: RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
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#define: RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
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#define: RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
RCC_APB1_APB2_clock_source
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#define: RCC_HCLK_Div1 ((uint32_t)0x00000000)
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#define: RCC_HCLK_Div2 ((uint32_t)0x00000400)
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#define: RCC_HCLK_Div4 ((uint32_t)0x00000500)
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#define: RCC_HCLK_Div8 ((uint32_t)0x00000600)
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#define: RCC_HCLK_Div16 ((uint32_t)0x00000700)
RCC_APB1_Peripherals
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#define: RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
DocID023800 Rev 1
Reset and clock control (RCC)
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