ST STM32F31xx User Manual page 324

Reset and clock control (RCC)
18.2.7.4 RCC_PCLK1Config
Function Name
Function Description
Parameters
Return values
Notes
18.2.7.5 RCC_PCLK2Config
Function Name
Function Description
Parameters
Return values
Notes
324/584
details refer to section above "CPU, AHB and APB busses
clocks configuration functions").
void RCC_PCLK1Config ( uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).

RCC_HCLK : defines the APB1 clock divider. This clock is
derived from the AHB clock (HCLK). This parameter can be
one of the following values:

RCC_HCLK_Div1 :

RCC_HCLK_Div2 :

RCC_HCLK_Div4 :

RCC_HCLK_Div8 :

RCC_HCLK_Div16 :

None.

None.
void RCC_PCLK2Config ( uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).

RCC_HCLK : defines the APB2 clock divider. This clock is
derived from the AHB clock (HCLK). This parameter can be
one of the following values:

RCC_HCLK_Div1 :

RCC_HCLK_Div2 :

RCC_HCLK_Div4 :

RCC_HCLK_Div8 :

RCC_HCLK_Div16 :

None.

None.
DocID023800 Rev 1
APB1 clock = HCLK
APB1 clock = HCLK/2
APB1 clock = HCLK/4
APB1 clock = HCLK/8
APB1 clock = HCLK/16
APB2 clock = HCLK
APB2 clock = HCLK/2
APB2 clock = HCLK/4
APB2 clock = HCLK/8
APB2 clock = HCLK/16
UM1581