Instruction Execution Timing - Atmel ATmega48A Manual

7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
7.6

Instruction Execution Timing

8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
Bit 15
0x3E (0x5E) SP15 SP14
0x3D (0x5D) SP7
7
Read/Write R/W
R/W
Initial Value RAMEND RAMEND
RAMEND RAMEND
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 7-5. Single Cycle ALU Operation
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
14 13 12
SP13 SP12
SP6 SP5 SP4
6 5 4
R/W R/W R/W
R/W R/W R/W
RAMEND RAMEND
RAMEND RAMEND
, directly generated from the selected clock source for the
CPU
T1
T1
11 10 9
SP11 SP10 SP9
SP3 SP2 SP1
3 2 1
R/W R/W R/W
R/W R/W R/W
RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND
T2 T3
T2 T3
8
SP8 SPH
SP0 SPL
0
R/W
R/W
RAMEND
RAMEND
T4
T4
14