Atmel ATmega48A Manual page 243

22.9 Register Description
22.9.1 TWBR – TWI Bit Rate Register
22.9.2 TWCR – TWI Control Register
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in Figure
Figure 22-21. Possible Status Codes Caused by Arbitration
START
Own
Address / General Call
received
Direction
Bit 7
(0xB8) TWBR7
Read/Write R/W
Initial Value 0
• Bits 7...0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit" on page 223 for calculating bit rates.
Bit 7
(0xBC) TWINT
Read/Write R/W
Initial Value 0
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
22-21. Possible status values are given in circles.
SLA
Arbitration lost in SLA
No 38
Yes
Write 68/78
Read
B0
6 5 4
TWBR6 TWBR5 TWBR4
R/W R/W R/W
0 0 0
6 5 4
TWEA TWSTA TWSTO
R/W R/W R/W
0 0 0
Data
Arbitration lost in Data
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
3 2 1
TWBR3 TWBR2 TWBR1
R/W R/W R/W
0 0 0
3 2 1
TWWC TWEN –
R R/W R
0 0 0
STOP
0
TWBR0 TWBR
R/W
0
"Bit Rate Generator
0
TWIE TWCR
R/W
0
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