Atmel ATmega48A Manual page 207

21.4 SPI Data Modes and Timing
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
Table 21-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Synchronous Master
mode
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
f System Oscillator clock frequency
OSC
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095)
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 21-1. Data bits are shifted out and latched in on opposite edges of the XCKn
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in Table
all ongoing communication for both the Receiver and Transmitter.
Table 21-2. UCPOLn and UCPHAn Functionality-
UCPOLn UCPHAn
0 0
0 1
1 0
1 1
Equation for Calculating Baud
(1)
Rate
f
OSC
BAUD = -------------------------------------- -
(
2 UBRRn +
21-2. Note that changing the setting of any of these bits will corrupt
SPI Mode Leading Edge
0 Sample (Rising)
1 Setup (Rising)
2 Sample (Falling)
3 Setup (Falling)
Equation for Calculating UBRRn
Value
UBRRn =
)
1
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
f
OSC
------------------- - 1
–
2BAUD
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