Timing And Synchronization - Toshiba Strata DK40 Installation & Maintenance Manual

Timing and Synchronization

Ferrite Core
Install the Ferrite core provided with the RPRI cable kit (Part Code: 093-1050/02) as shown
in Figure
RPTU
Side View
2754
Figure 3-18
Timing and Synchronization
In the DK40, one PRI or BRI PCB must be programmed to extract the clock signal. It uses
the signal as the DK system Primary clock reference. The clock provider should be a reliable
source, such as a British Telecom. All other PRI or BRI lines connected to the DK40 will be
synchronized to the same clock provider. If the PRI or BRI are not synchronized to the same
clock provider, the DK40 could experience "slip" problems.
Timing reference assignments for PRI and BRI are made with the Program *42 series. The
timing or synchronization program determines how the DK40 digital voice or data
transmission path is synchronized with the far-end digital path. For proper PRI and BRI
operation, the equipment at each end of the line must be synchronized.
The CTU time switch is synchronized as the slave to the PRI or BRI line (Line 1 in
Figure 3-19). The DK40 PRI or BRI in any slot number can be assigned as the Primary
reference (Program *42-1, for this PRI or BRI).
If a malfunction occurs and Primary reference synchronization is lost, the DK40
automatically switches modes and synchronizes to the Secondary reference, provided that
Strata DK40 I&M Manual Spring 1999
Refer to the Strata DK40 Programming Manual or DK Library CD-Rom for more details.
3-18. This core is needed to comply with EMC requirements.
ISDN PRI Jack
Tie Wrap
Ferrite Core Installation
DK40 Universal Slot PCBs
CAT5 Shielded Cable
Ferrite Core
Note: The Ferrite core must be
as close as possible to the RPTU.
One Turn
3-37