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Lattice Semiconductor
Table 12. FPGA I/O Test SMA Connectors (Continued)
SMA
Designation
Name
J49
URC_PLLC
J50
PCLKT3_1
J51
PCLKC3_1
High Speed Test Point
DP1
(see Appendix A, Figure 12)
General-purpose FPGA pins are available via a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
U18
(see Appendix A, Figure 11)
The LatticeSC Evaluation Board is equipped with an 84-BGA DDR2 SDRAM memory device such as a Micron
MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation board
includes termination of address and command signals. It includes all power and external components needed to
demonstrate the memory controller of the LatticeSC device.
Ordering Information
Description
LatticeSC PCI Express x4 Evaluation Board
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
techsupport@latticesemi.com
Internet:
www.latticesemi.com
Revision History
Date
July 2007
December 2007
September 2009
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
LFSC80 Signal
PR16B/URC_PLLT_IN_A
PR50C
PR50D
LFSC80E-P4-EV
Version
01.0
Initial release.
01.1
Updated FPGA Clock Management text section.
01.2
Updated On-Board Flash Memory text section.
LatticeSC PCI Express x4 Evaluation Board
1152
BGA
Termination Description
G5
50-ohm Ground Termination
U6
50-ohm Ground Termination
V6
50-ohm Ground Termination
Ordering Part Number
Change Summary
14
User's Guide
Termination
Resistor(s)
China RoHS Environment-Friendly
Use Period (EFUP)
10
R167
R168
R169
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