Commodore Amiga A500 Technical Reference Manual page 87

Override (IOVR)
bus also provides the encoded interrupt lines IIPLO, IIPLI, and IIPL2
on bus pins 40,42, and 44 respectively. These are useless as inputs,
but as outputs are required by any Coprocessor or alternate proces-
sor that needs to monitor system interrupts. In the A2000/B2000
scheme, coprocessors sit in the Coprocessor Slot which allows them
full control of the system. The encoded interrupt lines have been re-
placed with decoded interrupt lines that may be freely used as inputs;
interrupt levels
7
(/EINT7), 5 (IEINTS), and 4 (lEINT4) are available
now on bus pins 40,42, and
44
respectively, and the level 1 inter-
rupt (IEINT1) is available on bus pin 96 (which is left open in the
ZORRO specification). See Appendix for pin list.
The IOVR, or Override, signal is a special Amiga expansion signal that
can serve two purposes. The signal can basically turn off the on-
board decoding of system memory ranges, including those used by
the Amiga custom chips.
As
a result of this, it can also turn off inter-
nally generated things, like IDTACK.
The timing in the
A500
and 82000, based on the Gary chip (not the
PALS of the older machines) effectively prohibits the use of OVR* for
the area outside of $200000 to S9FFFFF. Due to the buffering de-
lays of the Expansion Bus, this signal should never be used for over-
lay on a Plc.
The other use of this signal is better supported. Asserting IOVR will
tri-state the internally generated IDTACK signal, allowing a Co-
processor or Expansion device to create its own IDTACK. The same
effect can be achieved for most applications by using XRDY to delay
the motherboard's generation of IDTACK. Pin
17.
External Ready
(XRDY)
This input provides a way for an external device to delay the mother-
board generated IDTACK, for things like slow memory and 110
boards that need to add wait states. This signal should be negated
very quickly, no later than 60ns from address valid (/AS asserted), in
order for the motherboard circuitry to have enough time to prevent
the normal assertion of IDTACK. XDRY should stay negated for as
many wait states are required. Once XRDY is asserted. IDTACK com-
pletes the rest of the normal cycle. XRDY is a wired-OR input; it is
pulled up by a resistor on the motherboard, and should be driven
with an open collector or equivalent output. Pin 18.