Commodore Amiga A500 Technical Reference Manual page 28

Read or Write Cycle
A PIC as master must drive the bus using the same protocol as the
with
a PIG as Master 68000. Some of the timing margins must be better than those from
the 68000, because the PIC is driving through several levels of buff-
ers, and the Amiga logic is designed t o the
68000 (8
megahertz
part) specs. Specific timing requirements can be found in the tables
later in this section.
Bus Arbitration
The bus arbitration scheme is based on the 68000 BR*,BG*,BGACK*
protocol. PlCs are required to assert BR* clocked by the rising edge
of 7 M . This makes it less expensive t o design bus arbitration logic
that will be reliable. Specifically, synchronous arbitration logic can be
clocked on 7 M without danger of going metastable.
SYSTEM LEVEL
ORGANIZATION (AND
Address Override (OVR*)
Pin 1 7 OVR* can only be used in between address $200000 and
A0000, and implies you have t o supply your own DTACK*. OVR* is
not supported for the purpose of disabling system decoding in the
COO000 t o DFFFFF range. Worst case 68000 timing requires modi-
fications t o the system decode gate array t o accomplish this reliably.
Other uses of OVR* are not supported.
INTERRUPTS
USE IN7"2+ OR INm* (DON'T
There are two interrupt input lines on the
PULL IPLO*-IPL2*)
Amiga: INTZ* and INT6*. INTZ*
=
pin
19.
INT6*
=
in
22.
these lines assert
levels 2 and 6'to the processor
Do
not assert the IPLO* thru IPE* lines,
because they are already driven by
internal logic.