Commodore Amiga A500 Technical Reference Manual page 172

SCSl Controller
I 1 0 DEFINITIONS
In data recovery and error correction the ECC syndrome must be
stable in order t o perform a correction. This insures that multiple at-
tempts are made to recover marginal data before correction data is
applied and further reduces the probability of miscorrection on long
(greater than 12-bit) error bursts.
The significance of not correcting data unless the ECC syndrome
is
stable is that 1) noise induced errors are not corrected and 2 ) real
errors are corrected quickly without wasting time on useless retries.
The user can improve data reliability by mapping tracks with flaws
and by reducing the error correction span. The latter reduces the
odds of mis-correction on large errors (greater than 12 bits) and
provides for early detection of a degrading media. The controller can
be programmed to report or not report "soft" errors, on reads that
took multiple tries but did not need correction.
Monitoring soft errors is probably the best method of early detec-
tion. A correction span of seven
(7)
bits is thereby suggested as an
optimum in data integrity. An alternate eleven (1 1 ) bit correction
span could be used as a means t o retrieve the data before the track is
mapped.
The SCSl controller uses the Western Digital WD33C93-SBIC which
provides the actual interface t o the SCSl connector and supports the
full SCSl protocol minimizing host responsibilities. The WD33C93 is
supported with a flexible architecture allowing either the 68000
(host) or the Z80A (board processor) t o control the WD33C93 oper-
ations. Data transfer can be done via DMA or host 110. For detailed
information refer to Western Digital WD33C93 manual.
The following 110 addresses refer only t o offset location since the ac-
tual board location in physical memory is configurable as described
elsewhere in this manual. Refer t o this manual for details on auto-
config 110 descriptions. 110 locations
0
hex through 4 2 hex are writ-
ten out as nybbles or 4 data bits (AD1 2-AD1 5). I10 addresses 50H
-
68H are unique t o this board and are described later in this docu-
ment.
Hex Location Definitions
00102 Boardtype and size
04/06 Product number
1011 2 Mfg
#
high and
14/16 low byte