Commodore Amiga A500 Technical Reference Manual page 53

Slave Bus Timing
CPU bus timing is based on an 8Mhz 68000, with only one excep-
tion: under normal operation, the bus control PAL asserts DTACK*
for you. D O NOT ASSERT DTACK*; do not attach any outputs to the
DTACK* line.
Details of 68000 timing are available in the Motorola 68000 hard-
ware manual. If you are designing a bus slave, most bus timing is per
the 68000 spec, except that the CPU will pull DTACK* for you.
If
you
need to delay our assertion of DTACK*, you must pull XRDY (Pin 18)
no later than 60ns after the assertion of AS*. You should release
XRDY when you are ready to complete the bus cycle.
Also remember that in the expansion architecture, data drivers
should not turn on during a Read cycle until
S4.
For those of you who have not designed anything on the
68K
bus be-
fore, this description is intended to make looking at the Motorola
timing diagrams easier. For more details and timing specs see
Motorola hardware manual (fold out timing diagrams in the back
of the book.)
See Figure 3.2 in this section. Motorola labels the states of the pro-
cessor clock SO-S7. The processor starts driving the address lines
during S1, and asserts AS* (Address Strobe) during S2.
If
the cycle is
a read, the data strobes (UDS*,LDS*) are asserted during S2 also
(they are delayed until
S4
on a write).
The board responds to AS* by asserting DTACK* (unless you delay
DTACK by pulling XRDY low). In order to run a normal
4
clock bus
cycle, DTACK* meets the setup time prior to S5. DTACK* is the ac-
knowledge to the bus cycle. If DTACK* is not asserted, the 68000
stays in the middle of the bus cycle until DTACK* (or BERR* or
VPA*) is asserted. Once DTACK* is asserted, the processor completes
the read (or write) and ends the cycle by disasserting the strobes
(AS*.UDS*,LDS*) and tri-stating its bus drivers.
If
the slave you are designing cannot respond fast enough to success-
fully complete a
4
clock bus cycle, it must pull XRDY low within 60ns
after the assertion of AS* (and of course the correct address). Our
board then will not assert DTACK* until you release XRDY. You
should drive XRDY with an open collector output; we provide a 1
K
pullup resistor on our board.