Commodore Amiga A500 Technical Reference Manual page 29

VPA
Is Not
Recommended
INTERRUPT LATENCY-
Interrupt latency on the Amiga is highly
BLIITER, MASKED INTS
application software dependent, this is
because the Blitter can be operated in
"nasty mode" at the software's option.
If
thi
blitter is "nasty" and is given a lot
of work to do, the processor receives
very few memory cycles, so the
interrupt latency will suffer.
The software can also mask out
interrupts using on-board interrupt
control logic.
We recommend that you design your peripherals t o run asynchro-
nously on the 68000 bus. that is. a slow peripheral should be mem-
ory mapped and use pulling XRDY low as a means of making the
68000
run a slower cycle. The use of XRDY to delay DTACK is dis-
cussed elsewhere in this document.
We do not recommend using VPA. If you decide t o use VPA, you
must pull OVR* low 30ns before asserting VPA* low. Pulling OVR*
low will tri-state VPA* in the current design PAL, thus allowing your
logic to drive VPA*. Pulling OVR* will also prevent DTACK* from
being asserted by the PAL. However, this will not disable the on-
board 8 5 2 0 CIA chips.
If your slave uses the VPA VMA protocol t o be synchronous with the
68000's E clock, you must only use addresses in which A1 2 and A1 3
are high. This is because we have synchronous ports on board which
are activated by (A12* AND VMA), also (A13* AND VMA).
DO N o t U s e Pins Marked
Do not drive or load pins marked EXP or RESERVE.
EXP
TIMING GENERAL
DISCUSSION
Timing specifications are listed in Table 3-1
There are two main problems to be dealt with in the expansion archi-
tecture timing: propagation delays and skews in the clock, address.
data, and control paths. The timing is tight; thus, we recommend us-
ing FAST and AS parts to buffer these lines. To guarantee meeting
the timing requirements, you must be careful to not exceed the rec-
ommended operating conditions of the parts you chose, for example
the capacitive loading. In calculating your loading, note that all PlCs
are specified to present no more than two "F" loads plus minimal
trace capacitance to each connector pin. Backplanes are specified to
present no more than one "F" load plus trace capacitance t o the
Amiga. Do not use "typical" numbers; reliable systems can be built by
using "worst case" numbers.