Commodore Amiga A500 Technical Reference Manual page 178

contains
E 0
or AO, before attempting to clear the FlFO and retrans-
mit the block of data, if necesssary. If the FlFO cannot be cleared
after within 2 0 mS, the command will be terminated in the normal
manner, if possible.
Step 3: Reading The
If byte 1 2 is an FF, the rest of the command block is retrieved by the
Command Block
CMD. This requires the execution of Step 1 (LDO only) followed by
Step
2
four times. The data value for state DE of Step 1 is incre-
mented from 0 0 to
03,
by the HDC for each word transfer to get all
eight command bytes.
Step 4: Data Block
Transfer
Step S: Command
Completion
COMMANDS
Command Block
Block transfers are initiated as in Step 1 except that the third state
loaded is FE. The state DE was a single word transfer. The direction
of transfer is determined by data line DATA7 when initializing the
high order address lines. Status is read by the HDC at the end of
every block or word transfer, and a t the start of every new com-
mand.
To complete a command status must be returned to the host. The
status information returned is that defined by the 'Request Sense'
command. To do this, 2 status words must be transferred t o the
command block. The host DMA is setup for a word transfer, by set-
ting the LD2. LD1, and the LDO counters similar t o the read of the
command block byte 1 2 (see Step
1).
The four status bytes: ERROR
CODE, LUN:LADD2, LADDl, and LADDO are loaded into the FlFO on
the rising edge of PCSD-, a word a t a time. As usual, the DMA status
is examined, between word transfers. If the command. just executed
by the HDC required a disk access, then the ADV (address valid) bit is
set. Otherwise ADV
=
0 to indicate that the LSA, reported in the 4
byte statcs block, is meaningless. This completes the instruction. The
host is acknowledged by writing state BF to set the host vectored in-
terrupt line low. Also IREQ- is deasserted by the HDC.
In the 68000 memory located a t an address determined by Amiga
DOS is a 1 6 byte command block. The first byte received through the
FIFO is the MSB even byte, followed by the LSB odd byte. During the
command block transfer phase,
8
bytes specifying the command are
read by the HDC. The command block is organized as follows: