Commodore Amiga A500 Technical Reference Manual page 222

INTERFACE SIGNALS
02-Clock Input
The 0 2 clock is a TT1 compatible input used for internal device oper-
ation and as a timing reference for communicating with the system
data bus.
CS-Chip Select Input
The CS input controls the activity of the 8520. A low level on CS
while 0 2 is high causes the device t o respond t o signals on the R/W
and address (RS) lines. A high on CS prevents these lines from con-
trolling the 8520. The CS line is normally activated (low) a t 0 2 by
the appropriate address combination.
M - R e a m r i t e Input The
F U W
signal is normally supplied by the microprocessor and con-
trols the direction of data transfers of the 8520.
A
high on R/W indi-
cates a read (data transfer out of the 8520). while a low indicates a
write (data transfer into the 8520).
RS3-RSO - Address
The address inputs select the internal registers as described by the
Inputs
Register Map.
DB7-DBO
-
Bus The eight bit data bus transfers information between the 8 5 2 0 and
Inputs/o~tputs the system data bus. These pins are high impedance inputs unless CS
is low and
FUW
and 0 2 are high, t o read the device. During this read,
the data bus output buffers are enabled, driving the data from the
selected register onto the system data bus.
1RQ-Intempt Request IRQ is an open drain output normally connected t o the processor in-
output
terrupt input. An external pullup resistor holds the signal high, allow-
ing multiple IRQ-outputs t o be connected together. The IRQ output
is normally off (high impedance) and is activated low as indicated in
the functional description.
RES-Reset Input
A low on the RES pin resets all internal registers. The port pins are
set as inputs and port registers t o zero (although a read of the ports
will return all highs because of passive pullups). The timer control
registers are set t o zero and the timer latches t o all ones. All other
registers are reset t o zero.